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Details

Name: usb_host_core
Created: Jul 12, 2015
Updated: Apr 23, 2019
SVN Updated: Apr 23, 2019
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star2you like it: star it!

Other project properties

Category:Communication controller
Language:Verilog
Development status:Stable
Additional info:Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: GPL

USB 1.1 Host Controller

This IP core is a cutdown USB host controller which allows communications with full-speed (12mbps) USB devices.

The IP is accessed via an AXI4-Lite slave register interface for control, status and data.

Data to be sent or received is stored in some internal FIFOs. The data is accessed through the AXI4-Lite slave port. There is no DMA engine (e.g. a bus mastering interface) associated with this IP.

The core functions well, is very small, but is fairly inefficient in terms of CPU cycles required to perform USB transfers. This core is not compliant with any standard USB host interface specification, e.g OHCI or EHCI.

Instantiation

Instance usbh_host and hookup to UTMI PHY interface and a AXI4-Lite master (e.g. from your CPU). The core requires a 48MHz/60MHz clock input, which the AXI4-Lite and UTMI interfaces are expected to be synchronous to.

Limitations
  • Only tested for USB-FS (Full Speed / 12Mbit/s) only.
  • AXI4-L address and data must arrive in the same cycle.
Testing

Verified under simulation and on FPGA with various USB devices attached (hubs, mass storage, network devices).

References
Configuration
  • SOF_THRESHOLD - Number of clock cycles per millisecond (default: 48000 for 48MHz)
  • CLKS_PER_BIT - Number of clock cycles per FS bit (default: 4 for 48MHz)
Size / Performance

With the default configuration...

  • the design contains 317 registers, 392 LUTs (Xilinx ISE - Spartan 6)
  • synthesizes to more than the required 48MHz on a Xilinx Spartan 6 LX9 (speed -3)
Register Map
OffsetNameDescription
0x00USB_CTRLRW Control of USB reset, SOF and Tx FIFO flush
0x04USB_STATUSR Line state, Rx error status and frame time
0x08USB_IRQ_ACKW Acknowledge IRQ by setting relevant bit
0x0cUSB_IRQ_STSR Interrupt status
0x10USB_IRQ_MASKRW Interrupt mask
0x14USB_XFER_DATARW Tx payload transfer length
0x18USB_XFER_TOKENRW Transfer control info (direction, type)
0x1cUSB_RX_STATR Transfer status (Rx length, error, idle)
0x20USB_WR_DATAW Tx FIFO address for write data
0x20USB_RD_DATAR Tx FIFO address for read data
Register: USB_CTRL
BitsNameDescription
7PHY_DMPULLDOWNUTMI PHY D+ Pulldown Enable
6PHY_DPPULLDOWNUTMI PHY D+ Pulldown Enable
5PHY_TERMSELECTUTMI PHY Termination Select
4:3PHY_XCVRSELECTUTMI PHY Transceiver Select
2:1PHY_OPMODEUTMI PHY Output Mode
1TX_FLUSHFlush Tx FIFO
0ENABLE_SOFEnable SOF (start of frame) packet generation
Register: USB_STATUS
BitsNameDescription
31:16SOF_TIMECurrent frame time (0 - 48000)
2RX_ERRORRx error detected (UTMI). Clear on new xfer.
1:0LINESTATE_BITSLine state (1 = D-, 0 = D+)
Register: USB_IRQ_ACK
BitsNameDescription
3DEVICE_DETECTInterrupt on device detect (linestate != SE0).
2ERRInterrupt on error conditions.
1DONEInterrupt on transfer completion.
0SOFInterrupt on start of frame.
Register: USB_IRQ_STS
BitsNameDescription
3DEVICE_DETECTInterrupt on device detect (linestate != SE0).
2ERRInterrupt on error conditions.
1DONEInterrupt on transfer completion.
0SOFInterrupt on start of frame.
Register: USB_IRQ_MASK
BitsNameDescription
3DEVICE_DETECTInterrupt on device detect (linestate != SE0).
2ERRInterrupt on error conditions.
1DONEInterrupt on transfer completion.
0SOFInterrupt on start of frame.
Register: USB_XFER_DATA
BitsNameDescription
15:0TX_LENTx transfer data length
Register: USB_XFER_TOKEN
BitsNameDescription
31STARTTransfer start request
30ININ transfer (1) or OUT transfer (0)
29ACKSend ACK in response to IN data
28PID_DATAXDATA1 (1) or DATA0 (0)
23:16PID_BITSToken PID (SETUP=0x2d, OUT=0xE1 or IN=0x69)
15:9DEV_ADDRDevice address
8:5EP_ADDREndpoint address
Register: USB_RX_STAT
BitsNameDescription
31START_PENDTransfer start pending
30CRC_ERRCRC error detected
29RESP_TIMEOUTResponse timeout detected (no response)
28IDLESIE idle
23:16RESP_BITSReceived response PID
15:0COUNT_BITSReceived data count
Register: USB_WR_DATA
BitsNameDescription
7:0DATADate byte
Register: USB_RD_DATA
BitsNameDescription
7:0DATADate byte