MicroSimplez

Project maintainers

Details

Name: usimplez
Created: Mar 9, 2011
Updated: Nov 11, 2011
SVN Updated: Nov 9, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved

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Other project properties

Category:Processor
Language:VHDL
Development status:Stable
Additional info:Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

This project is developed at Reconfigurable Computer Laboratory - FRM - UTN, and allows
simulate and synthetize the Simplez processor. It is a didactic processor created by
Gregorio Fernández in his book "Conceptos Básicos de Arquitectura y Sistemas Operativos",
2003 Edition.

This theoretical processor has a von Neuman architecture, with a set of eight instructions
and 512 memory words. Each twelve bits word, contains two fields: operation code and
data address. Basically, Simplez repeats cyclically the next three steps:

- Reads the instruction stored in a main memory's address.
- Decodes the instruction and executes it.
- Generates the address in the main memory of the next instruction.