VHDL reads a file of instructions to perform Wishbone access, as if it's a wishbone master.
Used in testing a Wishbone peripheral with out having to instantiate and program a 'CPU' function
The aim is to have a text file with commands in it, which is the only bit that needs to be modified for different tests.
This test file is read in to the units, which runs the test.
- tested out with Modelsim 6.2g and Xilinx ISE 9.2 sp4
First bits of VHDL put into CVS.
Have in package commands
W32 and R32 for 32 bit reads and writes.
BKW32 and BKR32 for block read and write.
RMW32 for read modify write.
Top level is wbtb_1m_1s.vhd
Commands can be added to wb_master.vhd
next stage is do add a multi master capability, and to respond to bus errors and time outs.
BTW: Please feel free to feed back what and how you think this should go. I can't promise to take all on board, but I'm flying blind here and making this up as I go along from scratch, with what I'd want.
Feed back welcome.