Lepetenok, Ruslan

AVR Core

Hi,

I am using this AVR core for some time in a working system and I have found a serious bug (sometimes the CPU restarts or hangs).

I could trace it back to the cp2en signal, mostly affecting the logic in pm_fetch_dec.v. If you have a jmp instruction (opcode 16'h940C) the cp2en signal can cause the Jump instruction either to jump to the opcode as a target address (i.e. address 940C) or either not jump at all. This depends on the concrete cycle, when the cp2en appears.

If have build a testbench (or a comple Xilinx project) illustrating the bug.

Best,
Marco

Bug caused by cp2en for JMP instructions

I've downloaded the Verilog (twice) but seem to be missing the code that declares: "avr_core_dft_wrapper". It is instantiated in uc_top_wrp_vlog.v (line 438).
Thanks

missing wrapper ?

reg_rd_in       : out std_logic_vector  (7 downto 0);
                               reg_rd_out      : in  std_logic_vector  (7 downto 0);
                               reg_rd_adr      : out std_logic_vector  (4 downto 0);
                               reg_rr_out      : in  std_logic_vector  (7 downto 0);
                               reg_rr_adr      : out std_logic_vector  (4 downto 0);
                               reg_rd_wr       : out std_logic;

WHY?

Do you have a detailed document file for the  source of AVR_CORE? I am a student,I am interested to study it,thank you!

FOR STUDY!!!!

Can you please tell that the AVR core you have designed is cycle accurate or not. 
Please see the following code
NOP
NOP
JMP RESET
Increment: 
INC R18
NOP
NOP
NOP
RET

RESET:
LDI R16,1
LDI R17,2
ADD R16,R17
NOP
NOP

When the first JMP occurs; the first instruction is LDI R16,1 but it takes 3 more cycle to execute it. If you compare it with AVR Studio this is not the case. In actual it has to consume 3 cycles to execute JMP instruction only. I have added NOPs before LDI but still LDI takes 3 cycles. Any explanation???
Regards

Cycle Accuracy of AVR

In my simulation,I found the instruction pair of "rcall" and "ret" has some bugs.
In Modelsim,after "rcall" the fuction, the instruction "ret" make the "pc" back to 0x0000, not the position after the "rcall" in the program. In "AVR studio" ,there is not this problem.
I have not analysed the source code carefully now, And I'll do it later.
Hope your reply!
Thank you! 
                                                         Yours
                                                         Mark
                                                        2008.2.27.

"ret"  bug

There are no files in cvs. Is this an dead project?!

Rick

No files in cvs

I am student. i want to study AVR core by FPGA.

AVR Core Study

AVR core Study

I will develop board tester by FPGA with 8 bits CPU.
8 bits CPU functions are command interpriter, 
UART control and bus control.

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AVR Core