Gisselquist, Dan

Double Clocked FFT Core

[WARNING] actual bit length 32 differs from formal bit length 28 for port 'i_left' (fftstage.v:215)
[WARNING] actual bit length 32 differs from formal bit length 28 for port 'i_right' (fftstage.v:216)

[WARNING] entry size 40 at cmem_256.hex:1 does not match memory width 38 (fftstage.v:118)

[WARNING] actual bit length 32 differs from formal bit length 30 for port 'i_left' (fftstage.v:215)
[WARNING] actual bit length 32 differs from formal bit length 30 for port 'i_right' (fftstage.v:216)

[WARNING] entry size 44 at cmem_32.hex:1 does not match memory width 42 (fftstage.v:118)
[WARNING] entry size 44 at cmem_16.hex:1 does not match memory width 42 (fftstage.v:118)

[WARNING] expression size 11 truncated to fit in target size 10
(bitreverse.v:80)

fftgen -f 512 -n 14 -k1 -p 100

Synthesis warnings

Modelsim gives warnings in simulation:

fftgen -f 512 -n 14 -k1 -p 100 -dir fft-core_f512_n14_k1_p100

** Warning: (vsim-3015) [PCDPC] - Port size (28) does not match connection size (32) for port 'i_left'. The port definition is at: ../src/hwbfly.v(68).
   Time: 0 ps  Iteration: 0  Instance: /dsp3_tb/dsp3_0/fftmain_0/stage_512/HWBFLY/bfly File: ../src/fftstage.v Line: 214
** Warning: (vsim-3015) [PCDPC] - Port size (28) does not match connection size (32) for port 'i_right'. The port definition is at: ../src/hwbfly.v(68).
   Time: 0 ps  Iteration: 0  Instance: /dsp3_tb/dsp3_0/fftmain_0/stage_512/HWBFLY/bfly File: ../src/fftstage.v Line: 214
** Warning: (vsim-3015) [PCDPC] - Port size (30) does not match connection size (32) for port 'i_left'. The port definition is at: ../src/hwbfly.v(68).
   Time: 0 ps  Iteration: 0  Instance: /dsp3_tb/dsp3_0/fftmain_0/stage_256/HWBFLY/bfly File: ../src/fftstage.v Line: 214
** Warning: (vsim-3015) [PCDPC] - Port size (30) does not match connection size (32) for port 'i_right'. The port definition is at: ../src/hwbfly.v(68).
   Time: 0 ps  Iteration: 0  Instance: /dsp3_tb/dsp3_0/fftmain_0/stage_256/HWBFLY/bfly File: ../src/fftstage.v Line: 214

Simulation warnings

Modelsim simulation output is all X's with valid inputs. Imaginary part periodically - every 256 clocks - outputs all 0's. It seems to work correctly in an FPGA though. There's probably something not being reset or initialized in the source.

fftgen -f 512 -n 14 -k1 -p 100 -dir fft-core_f512_n14_k1_p100

Simulation output is all X's

First let me thank you for all the work you put into this core. I like your method of generating a configurable core with a C++ program that has no dependencies!

I'm not sure if this is a bug or not but with iverilog there is an error from longbimpy.v. The error given is: "longbimpy.v:142: error: Concatenation operand "(LUTB)*((k)+('sd2))" has indefinite width.". Iverilog seems very strict with this. The core does compile with another simulator (Active-HDL) and seems to work correctly.

I think the syntax that causes the error is actually the replication operator (line 1218 of the c program) "genp, {{(LUTB*(k+2))}{1'b0}} };" should be "genp, {(LUTB*(k+2)){1'b0}} };" After making this change it compiles and simulates on both of my simulators.

Best regards

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Double Clocked FFT Core