Created: Feb 20, 2016
Updated: Jan 16, 2019
SVN Updated: Jan 11, 2019
Latest version: download
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Other project properties
A lightweight, open source 32-bit CPU IP core optimized for FPGA implementation.
- portability (described in behavioral VHDL-93, not tied to any particular vendor);
- 3-stage hazard-free pipeline;
- 256 registers implemented as a RAM block;
- a simple instruction set with only 30 distinct opcodes;
- separate instruction and data buses, optional instruction cache;
- WISHBONE compatibility;
- 8 interrupts with hardwired priorities;
- optional divider.
- synthesizable RTL description;
- automated verification environment (self-checking testbench);
- software tools (assembler/linker, disassembler) with source code.
LXP32 is distributed under the terms of the MIT license.
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