LXP32, a lightweight 32-bit CPU core

Description

LXP32 is a lightweight, open source and FPGA-friendly 32-bit CPU IP core. It uses a simple, original instruction set designed for straightforward FPGA implementation.

The main project home page is now on Github. This Opencores page may not be up to date.

Home page

Project home page on GitHub

Features

• portability (described in behavioral VHDL-93, not tied to any particular vendor);
• 3-stage hazard-free pipeline;
• 256 registers implemented as a RAM block;
• a simple instruction set with only 30 distinct opcodes;
• separate instruction and data buses, optional instruction cache;
• WISHBONE compatibility;
• 8 interrupts with hardwired priorities;
• optional divider.

Deliverables

• synthesizable RTL description;
• documentation;
• automated verification environment (self-checking testbench);
• software tools (assembler/linker, disassembler) with source code.

Note that there's no compiler backend for the LXP32 instruction set architecture yet.

Documentation

LXP32 Technical Reference Manual

Real-world usage

A few commercial precision motor control systems (link in Russian) are powered by the LXP32 processor.

License

LXP32 is distributed under the terms of the MIT license.