OpenCores

* LXP32, a lightweight 32-bit CPU core :: Overview



Project maintainers

Details

Name: lxp32
Created: Feb 20, 2016
Updated: Feb 7, 2019
SVN Updated: Jan 25, 2019
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 1 solved
Star0you like it: star it!

Other project properties

Category:Processor
Language:VHDL
Development status:Stable
Additional info:Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: Others

Description

LXP32 is a lightweight, open source and FPGA-friendly 32-bit CPU IP core. It uses a simple, original instruction set designed for straightforward FPGA implementation.

Home page

LXP32 logo

Project home page on GitHub

Features

  • portability (described in behavioral VHDL-93, not tied to any particular vendor);
  • 3-stage hazard-free pipeline;
  • 256 registers implemented as a RAM block;
  • a simple instruction set with only 30 distinct opcodes;
  • separate instruction and data buses, optional instruction cache;
  • WISHBONE compatibility;
  • 8 interrupts with hardwired priorities;
  • optional divider.

Deliverables

  • synthesizable RTL description;
  • documentation;
  • automated verification environment (self-checking testbench);
  • software tools (assembler/linker, disassembler) with source code.

Note that there's no compiler backend for the LXP32 instruction set architecture yet.

Documentation

PDFLXP32 Technical Reference Manual

Real-world usage

A few commercial precision motor control systems (link in Russian) are powered by the LXP32 processor.

License

LXP32 is distributed under the terms of the MIT license.

© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.