* LXP32, a lightweight 32-bit CPU core

Project maintainers


Name: lxp32
Created: Feb 20, 2016
Updated: Sep 6, 2022
SVN Updated: Sep 6, 2022
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 1 solved
Star5you like it: star it!

Other project properties

Development status:Stable
Additional info:Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: B.3
License: Others


LXP32 is a lightweight, open source and FPGA-friendly 32-bit CPU IP core. It uses a simple, original instruction set designed for straightforward FPGA implementation.

The main project home page is now on Github. This Opencores page may not be up to date.

Home page

LXP32 logo

Project home page on GitHub


  • portability (described in behavioral VHDL-93, not tied to any particular vendor);
  • 3-stage hazard-free pipeline;
  • 256 registers implemented as a RAM block;
  • a simple instruction set with only 30 distinct opcodes;
  • separate instruction and data buses, optional instruction cache;
  • WISHBONE compatibility;
  • 8 interrupts with hardwired priorities;
  • optional divider.


  • synthesizable RTL description;
  • documentation;
  • automated verification environment (self-checking testbench);
  • software tools (assembler/linker, disassembler) with source code.

Note that there's no compiler backend for the LXP32 instruction set architecture yet.


PDFLXP32 Technical Reference Manual

Real-world usage

A few commercial precision motor control systems (link in Russian) are powered by the LXP32 processor.


LXP32 is distributed under the terms of the MIT license.