* NEO430 Processor (MSP430-compatible)

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Name: neo430
Created: Oct 16, 2015
Updated: Jun 23, 2020
SVN Updated: May 18, 2020
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 3 reported / 3 solved
Star19you like it: star it!

Other project properties

Development status:Stable
Additional info:Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: B.4
License: BSD

The NEO430 Processor

Build Status license release documentary

issues pull requests last commit processor status

Table of Content


Welcome to The NEO430 Processor project!

You need a small but still powerful, customizable and microcontroller-like processor system for your next FPGA project? Then the NEO430 is the right choice for you.

This processor is based on the Texas Instruments MSP430(TM) ISA and provides compatibility with the original instruction set (see differences below). The NEO430 is not an exact MSP430 clone – it is more like a complete new implementation from the bottom up. The processor features a very small outline, already implementing standard features like a timer, a watchdog, UART, TWI and SPI serial interfaces, general purpose IO ports, an internal bootloader and of course internal memory for program code and data. All of the implemented peripheral modules are optional – so if you do not need them, you can exclude them from synthesis to reduce the size of the system. Any additional modules, which make a more customized system, can be connected via a Wishbone-compatible bus interface or directly implemented within the processor. By this, you can built a system, that perfectly fits your needs.

It is up to you to use the NEO430 as stand-alone, configurable and extensible microcontroller, or to use it as controller within a more complex SoC design.

The high-level software development is based on the free TI msp430-gcc compiler tool chain. You can either use Windows (PowerShell or Linux Subsystem) or Linux as build environment for your applications – the project supports both worlds.

This project is intended to work "out of the box". Just synthesize the test setup from this project, upload it to your FPGA board of choice (the NEO430 uses a FPGA vendor-independent VHDL description) and start exploring the capabilities of the NEO430 processor. Application program generation works by executing a single "make" command. Jump to the "Let’s Get It Started" chapter in the NEO430 documentary, which provides a lot of guides and tutorials to make your first NEO430 setup run: NEO430 Datasheet NEO430 Datasheet

Want to go further? Check out the big brother of the NEO430: The RISC-V powered 32-bit NEORV32.

Processor Features

NEO430 Overview

(optional modules are marked using dashed lines in the figure above)

  • 16-bit open source soft-core microcontroller-like processor system
  • Full support of the original MSP430 instruction set architecture
  • Code-efficient CISC-like instruction capabilities
  • Tool chain based on free TI msp430-gcc compiler (also available here on github)
  • Application compilation scripts (makefiles) for Windows Powershell / Windows Subsystem for Linux / native Linux
  • Software requirements (regardless of platform):
    • TI msp430-gcc compiler
    • native GCC compiler
    • GNU Make
  • Completely described in behavioral, platform-independent VHDL (no macros, primitives, attributes, etc. used)
  • Fully synchronous design, no latches, no gated clocks
  • Very low resource requirements and high operating frequency
  • Internal DMEM (RAM, for data) and IMEM (RAM or ROM, for code), configurable sizes
  • Customizable processor hardware configuration:
    • Optional multiplier/divider unit (MULDIV)
    • Optional high-precision timer (TIMER)
    • Optional universal asynchronous receiver and transmitter (UART)
    • Optional serial peripheral interface master (SPI), 8 or 16 bit transfer data size, 6 dedicated chip-select lines
    • Optional I2C-compatible two wire serial interface master (TWI) supporting clock stretching
    • Optional general purpose parallel IO port (GPIO), 16 inputs & 16 outputs, with pin-change interrupt and PWM option
    • Optional 32-bit Wishbone bus master interface adapter (WB32) - including bridges to Avalon (TM) bus and AXI4-Lite (TM)
    • Optional watchdog timer (WDT)
    • Optional cyclic redundancy check unit (CRC16/32)
    • Optional custom functions unit (CFU) for processor-internal user-defined processor extensions
    • Optional 4 channel PWM controller with 4 or 8 bit resolution (PWM)
    • Optional Galois Ring Oscillator (GARO) based true random number generator (TRNG) with de-biasing and internal post-processing
    • Optional external interrupts controller with 8 independent channels (EXIRQ), can also be used for software-triggered interrupts (traps, breakpoints, etc.)
    • Optional NCO-based programmable frequency generator (FREQ_GEN) with 3 independent output channels
    • Optional internal bootloader (2kB ROM) with serial user console and automatic application boot from external SPI flash (like the FPGA configuration storage)

Differences to the Original MSP430 Processors

  • Completely different processor modules with different functionality
  • Up to 48kB instruction memory and 12kB data memory
  • NEO430 tool chain (makefiles, boot-code and linker script) required for application compilation
  • Custom binary executable format
  • No hardware debugging interface
  • No analog components
  • No support of TI's Code Composer Studio
  • No support of CPU's DADD operation
  • Implicit software support of the NEO430 multiplier only via experimental ABI-override mode**
  • Just 4 CPU interrupt channels (can be extended via the external IRQ controller)
  • Single clock domain for complete processor
  • Different numbers of instruction execution cycles
  • Only one power-down (sleep) mode

*) A quite promising experimental mode to allow implicit multiplier usage (just write AB in your code and the compiler will automatically utilize the multiplier unit for this)

Top Entity

The top entity of the processor is neo430_top.vhd (from the rtl\core folder). Just instantiate this file in your project and you are ready to go! All signals of this top entity are of type std_ulogic or std_ulogic_vector, respectively. If you need a top entity with resolved signals (std_logic), take a look at the top_templates folder. These alternative top entities also support AXI or Avalon connectivity.


The main features and the actually implemented peripheral modules are configured via the top unit's generics.

Generic NameTypeDefault ValueFunction
CLOCK_SPEEDnatural100000000Clock speed of CPU clock input "clk_i" in Hz
IMEM_SIZEnatural4*1024Size of internal instruction memory in bytes (max 48 kB)
DMEM_SIZEnatural2*1024Size of internal data memory in bytes (max 12 kB)
USER_CODEstd_ulogic_vector(15:0)x"0000"16-bit custom user code, can be read by user software
MULDIV_USEbooleantrueImplement multiplier/divider unit (MULDIV)
WB32_USEbooleantrueImplement Wishbone interface adapter (WB32)
WDT_USEbooleantrueImplement watchdog timer (WDT)
GPIO_USEbooleantrueImplement general purpose parallel in/out port (GPIO)
TIMER_USEbooleantrueImplement high-precision timer (TIMER)
UART_USEbooleantrueImplement UART serial communication unit (UART)
CRC_USEbooleantrueImplement checksum computation unit (CRC16/32)
CFU_USEbooleanfalseImplement custom functions unit (CFU)
PWM_USEbooleantrueImplement pulse width controller (PWM)
TWI_USEbooleantrueImplement two wire serial interface unit (TWI)
SPI_USEbooleantrueImplement serial peripheral interface unit (SPI)
TRNG_USEbooleanfalseImplement true random number generator (TRNG)
EXIRQ_USEbooleantrueImplement external interrupts controller (EXIRQ)
FREQ_GEN_USEbooleantrueImplement programmable frequency generator (FREQ_GEN)
BOOTLD_USEbooleantrueImplement and auto-start internal bootloader
IMEM_AS_ROMbooleanfalseImplement internal instruction memory as read-only


Regarding unused unit's signals: Connect all unused inputs to low and leave all unused outputs 'open'. Signal driections are seen from the processor.

Signal NameWidthDirectionHW UnitFunction
clk_i1In-Global clock line; all FFs triggering on rising edge
rst_i1In-Global reset, low-active
gpio_o16OutGPIOGeneral purpose parallel output
gpio_i16InGPIOGeneral purpose parallel input
pwm_o4OutPWMPulse width modulation channels
timer_fg_o1OutFREQ_GENProgrammable frequency generator output
uart_txd_o1OutUARTUART serial transmitter
uart_rxd_i1InUARTUARt serial receiver
spi_sclk_o1OutSPISPI master clock
spi_mosi_o1OutSPISPI serial data output
spi_miso_i1InSPISPI serial data input
spi_cs_o8OutSPISPI chip select lines (active-low)
twi_sda_io1InOutTWITWI master serial data line (external pull-up required)
twi_scl_io1InOutTWITWI master serial clock line (external pull-up required)
wb_adr_o32OutWB32Wishbone slave address
wb_dat_i32InWB32Wishbone write data
wb_dat_o32OutWB32Wishbone read data
wb_we_o1OutWB32Wishbone write enable
wb_sel_o1OutWB32Wishbone byte enable
wb_stb_o1OutWB32Wishbone strobe
wb_cyc_o1OutWB32Wishbone valid cycle
wb_ack_i1InWB32Wishbone transfer acknowledge
ext_irq_i8InEXIRQInterrupt request lines, high-active
ext_ack_o8OutEXIRQInterrupt acknowledge, high-active, single-shot

FPGA Implementation Results

Mapping results generated for HW version 0x0406. The full (default) hardware configuration includes all optional processor modules (excluding the CFU and the TRNG), an IMEM size of 4kB and a DMEM size of 2kB. The minimal configuration only includes the CPU (including IMEM and DMEM) and the GPIO module. Results generated with Xilinx Vivado 2019.2, Intel Quartus Prime Lite 17.1 and Lattice Radiant 1.1 (Synplify)

Xilinx Artix-7 (XC7A35TICSG324-1L)LUTsFFsBRAMsDSPsf_max*
Full (default) configuration:1036 (5%)1144 (2.75%)2.5 (5%)0 (0%)100 MHz
Minimal configuration (CPU + GPIO):576 (3%)266 (0.6%)1 (2%)0 (0%)100 MHz
Intel Cyclone IV (EP4CE22F17C6)LUTsFFsMemory bitsDSPsf_max
Full (default) configuration:1869 (8%)1137 (5%)65800 (11%)0 (0%)121 MHz
Minimal configuration (CPU + GPIO):590 (3%)230 (1%)49408 (8%)0 (0%)122 MHz
Lattice iCE40 UltraPlus** (iCE40UP5K-SG48I)LUTsFFsEBRsDSPsSPRAMsf_max*
Full (default) configuration:3928 (74%)1923 (36%)9 (30%)0 (0%)2 (50%)20.25 MHz
Minimal configuration (CPU + GPIO + Bootloader):1812 (34%)755 (14%)4 (13%)0 (0%)2 (50%)20.25 MHz

*) Constrained

**) Using optimized memory modules for IMEM (32kB) & DMEM (12kB) from the rtl\fpga_specific\lattice_ice40up folder

Device Utilization by Entity

The following table shows the required resources for each module of the NEO430 processor system. Note that the provided numbers only represent a coarse overview as logic elements might be merged and optimized beyond entity boundaries.

Mapping results generated for HW version 0x0406. The full (default) hardware configuration includes all optional processor modules (excluding the CFU but including the TRNG), an IMEM size of 4kB and a DMEM size of 2kB. Results were generated using Intel Quartus Prime Lite 17.1.

Intel Cyclone IV (EP4CE22F17C6)LUTsFFsMemory BitsDSPs
Bootloader Memory (Boot ROM, 2kB)21163840
Central Processing Unit (CPU)5251692640
Checksum Unit (CRC)1119400
Custom Functions Unit (CFU)*----
Data Memory (DMEM, 2kB)51163840
External Interrupts Controller (EXIRQ)705500
Frequency Generator (FREQ_GEN)14013000
GPIO Port Unit (GPIO)504500
High-Precision Timer (TIMER)665700
Instruction Memory (IMEM, 4kB)51327680
Multiplier & Divider (MULDIV)20913400
Pulse-Width Modulation Unit (PWM)966600
Serial Peripheral Interface (SPI)825900
System Info Memory (SYSCONFIG)121100
True Random Number Generator (TRNG)927600
Two Wire Interface (TWI)784300
Universal Asynchronous Rx/Tx (UART)1309100
Watchdog Timer (WDT)533700
Wishbone Interface (WB32)12911700

*) Hardware requirements defined by user application

HW-SW Ecosystem

The NEO430 Processor project provides driver libraries for the CPU itself and all included peripheral modules. These libraries provide a certain level of hardware abstraction and allow an easy usage of the different hardware modules. Modules that cannot be used "explicitly" (like CPU modules or the different memories) are not listed below.

Hardware unitVHDL sourceC library sourceC library headerSW example project
Main CPU defines file--neo430.h-
Central Processing Unit (CPU)neo430_cpu.vhdneo430_cpu.cneo430_cpu.h-
Custom Functions Unit (CFU)neo430_cfu.vhdprovided by CFU designerprovided by CFU designerexample
Checksum Unit (CRC16/32)neo430_crc.vhdneo430_crc.cneo430_crc.hexample
External Interrupts Controller (EXIRQ)neo430_exirq.vhdneo430_exirq.cneo430_exirq.hexample
Frequency Generator (FREQ_GEN)neo430_freq_gen.vhdneo430_freq_gen.cneo430_freq_gen.hexample
IO Port Unit (GPIO)neo430_gpio.vhdneo430_gpio.cneo430_gpio.hexample
Multiplier & Divider (MULDIV)neo430_muldiv.vhdneo430_muldiv.cneo430_muldiv.hexample
Pulse-Width Modulation Unit (PWM)neo430_pwm.vhdneo430_pwm.cneo430_pwm.hexample
Serial Peripheral Interface (SPI)neo430_spi.vhdneo430_spi.cneo430_spi.hexample
High-Precision Timer (TIMER)neo430_timer.vhdneo430_timer.cneo430_timer.hexample
True Random Number Generator (TRNG)neo430_trng.vhdneo430_trng.cneo430_trng.hexample
Two Wire Interface (TWI)neo430_twi.vhdneo430_twi.cneo430_twi.hexample
Universal Asynchronous Rx/Tx (UART)neo430_uart.vhdneo430_uart.cneo430_uart.hexample
Watchdog Timer (WDT)neo430_wdt.vhdneo430_wdt.cneo430_wdt.hexample
Wishbone Interface (WB32)neo430_wb_interface.vhdneo430_wishbone.cneo430_wishbone.hexample

All software projects are compiled using an application makefile.


In contrast to most mainstream processors the NEO430 processor does not implement a "classic" pipelined instruction execution. Instead, a multi-cycle instruction execution scheme is used: Each single instruction is executed in a series of micro instructions requiring several clock cycles to complete. The main benefit of this execution style is the highly reduced logic overhead as no complex pipeline hazard detection and resolving logic is required. This makes the NEO430 even smaller - at the cost of a reduced IPC (instructions per cycle). Also, the MSP430 ISA is not really compatible to the classic (DLX/MIPS-like) pipeline scheme due to its complex operand and adressing modes (e.g., ALU operations executing directly on memory data). However, this concept allows the processor to use very dense and powerfull CISC-like operations.

Furthermore, the multi-cycle architecture features a very short crtitical path when compared to other (even 32-bit) processors. Thus, the NEO430 can operate at very high frequencies even on low-cost (e.g., +120MHz on an Intel Cyclone IV) and low-power FPGAs (e.g., +20MHz on a Lattice iCE40 UltraPlus) even without any area constraints.

Depending on the format / operand addressing mode of an instruction, the actual execution can take 3 to 10 clock cycles. If all possible instruction types and formats are executed in an equally distributed manner (this is the worst case), the average CPI (clock cycles per instruction) evaluates to 7.33 cycles/instruction resulting in 0.136 MIPS per MHz (again: worst case).

CoreMark Benchmark

The CoreMark CPU benchmark was executed on the NEO430 and is available in the sw/example/coremark project folder This benchmark tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.

Hardware: 100 MHz, 32kB IMEM, 12kB DMEM, HW verison 0x0407, peripherals used: TIMER, UART, MULDIV
Software: msp430-gcc 8.3.0 for Linux, MEM_METHOD is MEM_STACK, 2000 CoreMark iterations
Optimization/ConfigurationExecutable SizeCoreMark ScoreRelative Score
-Os12150 bytes6.570.065 CoreMarks/MHz
-O214600 bytes7.160.072 CoreMarks/MHz
-Os + NEO430_MULDIV*12118 bytes14.430.144 CoreMarks/MHz
-O2 + NEO430_MULDIV*14562 bytes17.680.176 CoreMarks/MHz
-Os + NEO430_MULDIV* (DSP**)12060 bytes15.630.156 CoreMarks/MHz
-O2 + NEO430_MULDIV* (DSP**)14510 bytes19.420.194 CoreMarks/MHz

*) These results were generated using the "NEO430_HWMUL_ABI_OVERRIDE" feature flag, which allows to map implicit multiplications in the source code via compiler primitives directly to the multiplier core of the MULDIV unit. For more information see chapter "Multiplier and Divider Unit (MULDIV)" of NEO430.pdf.

**) This setup uses the FPGA's embedded multipliers (DSP blocks) for the MULDIV's multiplier unit. The "NEO430_HWMUL_DSP" feature flag eliminates the wait cycles usually required to wait for the result generated by the default serial MULDIV multiplier core.

Even though a score of 6.57 can outnumber certain architectures and configurations (see the score table on the CoreMark homepage), the relative score of 0.065 coremarks per second might sound pretty low. True. But you have to keep in mind that benchmark was executed using only the resources of the CPU itself. The CPU consists of only ~520 Intel Cyclone IV LUTs and does not contain any sophisticated ALU operations like multiplication or barrel shifting. When including NEO430 MULDIV unit (using the "NEO430_HWMUL_ABI_OVERRIDE" feature and using embedded DSP blocks ("NEO430_HWMUL_DSP")) the CoreMark score is increased to 19.42. By explicitly using additional HW accelerators from the NEO430 ecosystem (e.g. the CRC unit) the performance can be further increased.

Quick Start

  • At first, get the most recent version the NEO430 Processor project from GitHub:

    • Clone the NEO430 repository using git from the command line (suggested for easy project updates via git pull):

      git clone
    • Or download the current version of this project as ZIP file:

  • Next, install the free MSP430-GCC compiler toolchain from the TI homepage (select the "compiler only" package according to your system OS):

  • Make sure GNU Make and a native GCC compiler are installed (double check for the newest versions)

  • Create a new HW project with your FPGA synthesis tool of choice. Add all files from the rtl\core folder to this project (and add them to a new library called "neo430").

  • Follow the instructions from the "Let's Get It Started" section of the NEO430 documentary: NEO430 Datasheet NEO430 Datasheet

  • This documentary will guide you to create a simple test setup, which serves as "hello word" FPGA demo:

NEO430 Test Example Setup

  • The NEO430 project also includes some example programs from which you can start your own application: SW example projects

  • Have fun! =)

Change Log

The official change log of this project can be found at the end of the NEO430 Datasheet NEO430 Datasheet.


If you have any questions, bug reports, ideas or if you are facing problems with the NEO430 or want to give some kinf of feedback, open a new issue or directly drop me a line:


If you are using the NEO430 Processor in some kind of publication, please cite it as follows:

S. Nolting, "The NEO430 Processor",

This is a hobby project released under the BSD 3-Clause license. No copyright infringement intended.

BSD 3-Clause License

Copyright (c) 2020, Stephan Nolting. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.


"MSP430" and "Code Composer Studio" are trademarks of Texas Instruments Corporation.

"Windows" is a trademark of Microsoft Corporation.

"Virtex", "Artix" and "Vivado" are trademarks of Xilinx Inc.

"Cyclone", "Quartus" and "Avalon Bus" are trademarks of Intel Corporation.

"iCE40 UltraPlus", "Lattice Radiant" and "Lattice Diamond" are trademarks of Lattice Semiconductor Corporation.

"AXI", "AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.

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