OpenCores

The NEORV32 Processor (RISC-V)

Project maintainers

Details

Name: neorv32
Created: Jun 23, 2020
Updated: Jul 20, 2020
SVN Updated: Apr 9, 2022
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 1 solved
Star11you like it: star it!

Other project properties

Category:Processor
Language:VHDL
Development status:Stable
Additional info:Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: B.4
License: BSD

NEORV32

The NEORV32 RISC-V Processor

datasheet (pdf) datasheet (html) userguide (pdf) userguide (html) doxygen Gitter

  1. Overview
  2. Features
  3. FPGA Implementation Results
  4. Performance
  5. Software Framework & Tooling
  6. Getting Started :rocket:

1. Overview

neorv32 Overview

The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz.

Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. Whenever an unexpected situation occurs the application code is informed via precise and resumable hardware exceptions.

:interrobang: Want to know more? Check out the project's rationale.

:books: For detailed information take a look at the NEORV32 online documentation. The latest pdf versions can be found here.

:label: The project's change log is available in CHANGELOG.md. To see the changes between official releases visit the project's release page.

:package: Exemplary setups targeting various FPGA boards and toolchains to get you started.

:kite: Supported by upstream Zephyr OS and FreeRTOS.

:bulb: Feel free to open a new issue or start a new discussion if you have questions, comments, ideas or if something is not working as expected. Or have a chat on our gitter channel. See how to contribute.

:rocket: Check out the quick links below or directly jump to the User Guide to get started setting up your NEORV32 setup!

Project Key Features

  • all-in-one package: CPU plus SoC plus Software Framework & Tooling
  • completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
  • highly extensible hardware - on CPU, SoC and system level
  • be as small as possible while being as RISC-V-compliant as possible
  • from zero to printf("hello world!"); - completely open source and documented
  • easy to use even for FPGA/RISC-V starters – intended to work out of the box

Status

release GitHub Pages \ Documentation riscv-arch-test Processor

The NEORV32 is fully operational. The processor passes the official RISC-V architecture tests, which are checked by the neorv32-verif repository. It can successfully run any C program (for example from the sw/example folder) including CoreMark and can be synthesized for any target technology - tested on Intel, Xilinx and Lattice FPGAs.

[back to top]

2. Features

The NEORV32 Processor provides a full-featured microcontroller-like SoC build around the NEORV32 CPU. By using generics the design is highly configurable and allows a flexible customization to tailor the setup according to your needs. The following list shows all available SoC module. Note that all those modules are optional.

CPU

  • 32-bit little-endian RISC-V single-core, pipelined/multi-cycle Von-Neumann architecture
  • configurable ISA extensions
  • compatible to subsets of the Unprivileged ISA Specification (Version 2.2) and the Privileged Architecture Specification (Version 1.12).
  • machine and user modes
  • implements all standard RISC-V exceptions/interrupts (including MTI, MEI & MSI)
  • 16-fast interrupt requests as NEORV32-specific extensions

Memory

  • processor-internal data and instruction memories (DMEM / IMEM) & cache (iCACHE)
  • pre-installed bootloader (BOOTLDROM) with serial user interface
    • allows booting application code via UART or from external SPI flash

Timers

  • machine system timer, 64-bit (MTIME), RISC-V spec. compatible
  • general purpose 32-bit timer (GPTMR)
  • watchdog timer (WDT)

Input / Output

  • standard serial interfaces (UART, SPI, TWI)
  • general purpose GPIO and PWM
  • smart LED interface (NEOLED) to directly control NeoPixel(TM) LEDs

SoC Connectivity

  • 32-bit external bus interface, Wishbone b4 compatible (WISHBONE)
    • wrappers for AXI4-Lite and Avalon-MM host interfaces
  • 32-bit stream link interface with up to 8 independent RX and TX links (SLINK) - AXI4-Stream compatible
  • external interrupts controller with up to 32 channels (XIRQ)

Advanced

  • true random number generator (TRNG)
  • execute in place module (XIP) to directly execute code from SPI flash
  • custom functions subsystem (CFS) for tightly-coupled custom accelerators and interfaces
  • custom functions unit (CFU) for up to 1024 custom RISC-V instructions

Debugging

  • on-chip debugger (OCD) accessible via standard JTAG interface
  • compliant to the "Minimal RISC-V Debug Specification Version 0.13.2"
  • compatible with OpenOCD + gdb and Segger Embedded Studio

:warning: The B, Zfinx and Zmmul RISC-V ISA extensions are frozen and officially ratified but there is no upstream gcc support yet (will be available with GCC12). To circumvent this, the NEORV32 software framework provides intrinsic libraries for the B and Zfinx extensions.

[back to top]

3. FPGA Implementation Results

Implementation results for exemplary CPU-only configuration generated for an Intel Cyclone IV E EP4CE22F17C6 FPGA using Intel Quartus Prime Lite 21.1 (no timing constrains, balanced optimization, fmax from _Slow 1200mV 0C Model).

CPU Configuration (version 1.6.9.8)LEsFFsMemory bitsDSPsf_max
rv32i_Zicsr132867810240128 MHz
rv32i_Zicsr_Zicntr161480810240128 MHz
rv32imac_Zicsr_Zicntr233899210240128 MHz

:bulb: An incremental list of the CPUs ISA extension's hardware utilization can found in the Data Sheet: FPGA Implementation Results - CPU.

The hardware resources used by a specific full-processor setup is defined by the implemented CPU extensions, the configuration of the peripheral modules and some "glue logic". Section FPGA Implementation Results - Processor Modules of the online datasheet shows the resource utilization of each optional processor module to allow an estimation of the actual setup's hardware requirements.

:bulb: The neorv32-setups repository provides exemplary FPGA setups targeting various FPGA boards and toolchains. The latest bitstreams and utilization reports for those setups can be found in the assets of the Implementation Workflow.

:bulb: The CPU & SoC provide further "tuning" options to optimize the design for maximum performance, maximum clock speed, minimal area or minimal power consumption: UG: Application-Specific Processor Configuration

[back to top]

4. Performance

The NEORV32 CPU is based on a two-stages pipeline architecture (fetch and execute). The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available CPU extensions.

The following table shows the performance results (scores and average CPI) for exemplary CPU configurations (no caches) executing 2000 iterations of the CoreMark CPU benchmark (using plain GCC10 rv32i built-in libraries only!).

CPU Configuration (version 1.5.7.10)CoreMark ScoreCoreMarks/MHzAverage CPI
small (rv32i_Zicsr)33.890.33894.04
medium (rv32imc_Zicsr)62.500.62505.34
performance (rv32imc_Zicsr + perf. options)95.230.95233.54

:bulb: More information regarding the CPU performance can be found in the Data Sheet: CPU Performance.

[back to top]

5. Software Framework and Tooling

  • core libraries for high-level usage of the provided functions and peripherals
  • application compilation based on GNU makefiles
  • gcc-based toolchain (pre-compiled toolchains available)
  • SVD file for advanced debugging and IDE integration
  • bootloader with UART interface console
  • runtime environment for handling traps
  • several example programs to get started including CoreMark, FreeRTOS and Conway's Game of Life
  • doxygen-based documentation, available on GitHub pages
  • supports implementation using open source tooling (GHDL, Yosys, nextpnr, ...) - both, software and hardware can be developed and debugged with open source tooling
  • continuous integration is available for:
    • allowing users to see the expected execution/output of the tools
    • ensuring specification compliance
    • catching regressions
    • providing ready-to-use and up-to-date bitstreams and documentation

:books: Want to know more? Check out Data Sheet: Software Framework.

[back to top]

6. Getting Started

This overview provides some quick links to the most important sections of the online Data Sheet and the online User Guide.

:electric_plug: Hardware Overview

:floppy_disk: Software Overview

:rocket: User Guide

license DOI

  • Overview - license, disclaimer, limitation of liability for external links, proprietary notice, ...
  • Citing - citing information

This is an open-source project that is free of charge. Use this project in any way you like (as long as it complies to the permissive license). Please quote it appropriately. :+1:

[back to top]


:heart: A big shout-out goes to the community and all the contributors, who helped improving this project!