The NEORV32 Processor (RISC-V)

Project maintainers


Name: neorv32
Created: Jun 23, 2020
Updated: Jul 20, 2020
SVN Updated: Mar 1, 2021
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
Star6you like it: star it!

Other project properties

Development status:Stable
Additional info:Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: B.4
License: BSD


The NEORV32 RISC-V Processor

Processor Check RISC-V Compliance license release


The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V-compliant NEORV32 CPU. The processor is intended as ready-to-go auxiliary processor within a larger SoC designs or as stand-alone custom microcontroller.

:books: For detailed information take a look at the NEORV32 data sheet (pdf). The doxygen-based documentation of the software framework is available online at GitHub-pages.

:label: The project’s change log is available as in the root directory of this repository. To see the changes between stable releases visit the project's release page.

:spiral_notepad: Check out the project boards for a list of current ideas, ToDos, features being planned and work being in-progress.

:bulb: Feel free to open a new issue or start a new discussion if you have questions, comments, ideas or bug-fixes. Check out how to contribute.

Key Features

  • RISC-V 32-bit rv32 NEORV32 CPU, compliant to
  • Configurable RISC-V-compliant CPU extensions
    • A - atomic memory access instructions (optional)
    • B - Bit manipulation instructions (optional)
    • C - compressed instructions (16-bit) (optional)
    • E - embedded CPU (reduced register file size) (optional)
    • I - base integer instruction set (always enabled)
    • M - integer multiplication and division hardware (optional)
    • U - less-privileged user mode (optional)
    • X - NEORV32-specific extensions (always enabled)
    • Zicsr - control and status register access instructions (+ exception/irq system) (optional)
    • Zifencei - instruction stream synchronization (optional)
    • PMP - physical memory protection (optional)
    • HPM - hardware performance monitors (optional)
  • Full-scale RISC-V microcontroller system / SoC NEORV32 Processor with optional submodules
    • optional embedded memories (instructions/data/bootloader, RAM/ROM) and caches
    • timers (watch dog, RISC-V-compliant machine timer)
    • serial interfaces (SPI, TWI, UARTs)
    • general purpose IO and PWM channels
    • external bus interface (Wishbone / AXI4)
    • subsystem for custom co-processors
    • more ...
  • Software framework
  • Full-blown data sheet (pdf)
  • Completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
  • Fully synchronous design, no latches, no gated clocks
  • Small hardware footprint and high operating frequency

Design Principles

  • From zero to hello_world: Completely open source and documented.
  • Plain VHDL without technology-specific parts like attributes, macros or primitives.
  • Easy to use – working out of the box.
  • Clean synchronous design, no wacky combinatorial interfaces.
  • Be as small as possible – but with a reasonable size-performance trade-off.
  • Be as RISC-V-compliant as possible.
  • The processor has to fit in a Lattice iCE40 UltraPlus 5k low-power FPGA running at 22+ MHz.


The processor is synthesizable (tested on real hardware using Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/Synplify Pro) and can successfully execute all the provided example programs including the CoreMark benchmark.

RISC-V Compliance: The processor passes the official rv32_m/C, rv32_m/I, rv32_m/M, rv32_m/privilege and rv32_m/Zifencei RISC-V compliance tests. More information regarding the NEORV32 port of the compliance framework can be found in riscv-compliance/

Project componentCI status
NEORV32 processorProcessor Check
SW Framework Documentation (online @GH-pages)Doc@GitHub-pages
Pre-built toolchainsTest Toolchains
RISC-V compliance testRISC-V Compliance


The full-blown data sheet of the NEORV32 Processor and CPU is available as pdf file: :page_facing_up: NEORV32 data sheet.

NEORV32 Processor Features

neorv32 Overview

The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup is highly customizable via the processor's top generics and already provides the following optional modules:

  • processor-internal data and instruction memories (DMEM / IMEM) & cache (iCACHE)
  • bootloader (BOOTLDROM) with UART console and automatic application boot from SPI flash option
  • machine system timer (MTIME), RISC-V-compliant
  • watchdog timer (WDT)
  • two independent universal asynchronous receivers and transmitters (UART0 & UART1) with optional hardware flow control (RTS/CTS)
  • 8/16/24/32-bit serial peripheral interface controller (SPI) with 8 dedicated chip select lines
  • two wire serial interface controller (TWI), with optional clock-stretching, compatible to the I²C standard
  • general purpose parallel IO port (GPIO), 32xOut & 32xIn, with pin-change interrupt
  • 32-bit external bus interface, Wishbone b4 compliant (WISHBONE)
  • wrapper for AXI4-Lite Master Interface (see AXI Connectivity)
  • PWM controller with 4 channels and 8-bit duty cycle resolution (PWM)
  • ring-oscillator-based true random number generator (TRNG)
  • custom functions subsystem (CFS) for tightly-coupled custom co-processor extensions
  • numerically-controlled oscillator (NCO) with three independent channels
  • system configuration information memory to check hardware configuration by software (SYSINFO)

NEORV32 CPU Features

The NEORV32 CPU is compliant to the official RISC-V specifications (2.2) including a subset of the RISC-V privileged architecture specifications (1.12-draft) tested via the official RISC-V Compliance Test Framework (see riscv-compliance/README).

More information regarding the CPU including a detailed list of the instruction set and the available CSRs can be found in the :page_facing_up: NEORV32 data sheet.

General Features

  • Modified Harvard architecture (separate CPU interfaces for data and instructions; NEORV32 processor: Single processor-internal bus via I/D mux)
  • Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme
  • No hardware support of unaligned accesses - they will trigger an exception
  • BIG-ENDIAN byte-order, processor's external memory interface allows endianness configuration to connect to system with different endianness
  • All reserved or unimplemented instructions will raise an illegal instruction exception
  • Privilege levels: machine mode, user mode (if enabled via U extension)
  • Official RISC-V open-source architecture ID

A - Atomic memory access extension

  • Supported instructions: LR.W (load-reservate) SC.W (store-conditional)

B - Bit manipulation instructions extension

  • :warning: Extension is not officially ratified yet by the RISC-V foundation!
  • Implies Zbb & Zbs sub-extensions (the remaining B sub-extensions are not supported yet)
  • Compatible to v0.94-draft of the bit manipulation spec
  • Support via intrisc library (see sw/example/bit_manipulation)
  • Zbb Base instruction set: CLZ CTZ CPOP SEXT.B SEXT.H MIN[U] MAX[U] ANDN ORN XNOR ROL ROR[I] zext(pseudo-instruction for PACK rd, rs, zero) rev8(pseudo-instruction for GREVI rd, rs, -8) orc.b(pseudo-instruction for GORCI rd, rs, 7)
  • Zbs Single-bit instructions: SBSET[I] SBCLR[I] SBINV[I] SBEXT[I]

C - Compressed instructions extension

  • Jump and branch instructions: C.J C.JAL C.JR C.JALR C.BEQZ C.BNEZ
  • Memory instructions: C.LW C.SW C.LWSP C.SWSP
  • System instructions: C.EBREAK (only with Zicsr extension)
  • Pseudo-instructions are not listed

E - Embedded CPU version extension

  • Reduced register file (only the 16 lowest registers)

I - Base integer instruction set

  • ALU instructions: LUI AUIPC ADD[I] SLT[I][U] XOR[I] OR[I] AND[I] SLL[I] SRL[I] SRA[I] SUB
  • Jump and branch instructions: JAL JALR BEQ BNE BLT BGE BLTU BGEU
  • Memory instructions: LB LH LW LBU LHU SB SH SW
  • System instructions: ECALL EBREAK FENCE
  • Pseudo-instructions are not listed

M - Integer multiplication and division hardware extension

  • Multiplication instructions: MUL MULH MULHSU MULHU
  • Division instructions: DIV DIVU REM REMU
  • By default, the multiplier and divider cores use an iterative bit-serial processing scheme
  • Multiplications can be mapped to DSPs via the FAST_MUL_EN generic to increase performance

U - Privileged architecture - User mode extension

  • Requires Zicsr extension
  • Privilege levels: M (machine mode) + less-privileged U (user mode)

X - NEORV32-specific CPU extensions

  • The NEORV32-specific extensions are always enabled and are indicated via the X bit set in the misa CSR.
  • 16 fast interrupt request channels with according control/status bits in mie and mip and custom exception codes in mcause
  • mzext CSR to check for implemented Z* CPU extensions (like Zifencei)
  • All undefined/umimplemented/malformed/illegal instructions do raise an illegal instruction exception

Zicsr - Privileged architecture - CSR access extension

  • Privilege levels: M-mode (Machine mode)
  • CSR access instructions: CSRRW[I] CSRRS[I] CSRRC[I]
  • System instructions: MRET WFI
  • Pseudo-instructions are not listed
  • Counter CSRs: [m]cycle[h] [m]instret[m] time[h] [m]hpmcounter*[h](3..31, configurable) mcounteren mcountinhibit mhpmevent*(3..31, configurable)
  • Machine CSRs: mstatus[h] misa(read-only!) mie mtvec mscratch mepc mcause mtval mip mvendorid marchid mimpid mhartid mzext(custom)
  • Supported (sync.) exceptions (all RISC-V-compliant):
    • Misaligned instruction address
    • Instruction access fault (via timeout/error after unacknowledged bus access)
    • Illegal instruction
    • Breakpoint (via ebreak instruction)
    • Load address misaligned
    • Load access fault (via timeout/error after unacknowledged bus access)
    • Store address misaligned
    • Store access fault (via unacknowledged bus access after timeout)
    • Environment call from U-mode (via ecall instruction in user mode)
    • Environment call from M-mode (via ecall instruction in machine mode)
  • Supported (async.) exceptions / interrupts:
    • Machine timer interrupt mti (via processor's MTIME unit / external signal), RISC-V-compliant
    • Machine software interrupt msi (via external signal), RISC-V-compliant
    • Machine external interrupt mei (via external signal), RISC-V-compliant
    • 16 fast interrupt requests (custom extension), 6+1 available for custom usage

Zifencei - Privileged architecture - Instruction stream synchronization extension

  • System instructions: FENCE.I (among others, used to clear and reload instruction cache)

PMP - Privileged architecture - Physical memory protection

  • Requires Zicsr extension
  • Configurable number of regions (0..63)
  • Additional machine CSRs: pmpcfg*(0..15) pmpaddr*(0..63)

HPM - Privileged architecture - Hardware performance monitors

  • Requires Zicsr extension
  • Configurable number of counters (0..29)
  • Additional machine CSRs: mhpmevent*(3..31) [m]hpmcounter*[h](3..31)

:warning: Non-RISC-V-Compliant Issues and Limitations

  • CPU and Processor are BIG-ENDIAN, but this should be no problem as the external memory bus interface provides big- and little-endian configurations
  • misa CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime; for compatibility: write accesses (in m-mode) are ignored and do not cause an exception
  • The physical memory protection (PMP) only supports NAPOT mode yet and a minimal granularity of 8 bytes
  • The A extension only implements lr.w and sc.w instructions yet. However, these instructions are sufficient to emulate all further AMO operations
  • The mcause trap code 0x80000000 (originally reserved in the RISC-V specs) is used to indicate a hardware reset (as "non-maskable interrupt")
  • The bit manipulation extension is not yet officially ratified, but is expected to stay unchanged. There is no software support in the upstream GCC RISC-V port yet. However, an intrinsic library is provided to utilize the provided bit manipulation extension from C-language code (see sw/example/bit_manipulation). NEORV32's B extension is compliant to spec. version "0.94-draft".

FPGA Implementation Results


This chapter shows exemplary implementation results of the NEORV32 CPU for an Intel Cyclone IV EP4CE22F17C6N FPGA on a DE0-nano board. The design was synthesized using Intel Quartus Prime Lite 20.1 ("balanced implementation"). The timing information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration of the CPU's generics is assumed (e.g. no physical memory protection, no hardware performance monitors). No constraints were used at all.

Results generated for hardware version

CPU ConfigurationLEsFFsMemory bitsDSPsf_max
rv32i97940910240123 MHz
rv32i + Zicsr178984710240122 MHz
rv32im + Zicsr2381112510240122 MHz
rv32imc + Zicsr2608114010240122 MHz
rv32imac + Zicsr2621114410240122 MHz
rv32imacb + Zicsr3013131010240122 MHz
rv32imacb + Zicsr + u3031131310240122 MHz
rv32imacb + Zicsr + u + Zifencei3050131310240116 MHz

Setups with enabled "embedded CPU extension" E show the same LUT and FF utilization and identical f_max as the according I configuration. However, the size of the register file is cut in half.

NEORV32 Processor-Internal Peripherals and Memories

Results generated for hardware version

ModuleDescriptionLEsFFsMemory bitsDSPs
BOOT ROMBootloader ROM (default 4kB)3132 7680
BUSSWITCHBus mux for CPU instr. & data interfaces65800
i-CACHEProc.-int. nstruction cache (default 1x4x64 bytes)2341568 1920
CFSCustom functions subsystem----
DMEMProcessor-internal data memory (default 8kB)6265 5360
GPIOGeneral purpose input/output ports676500
IMEMProcessor-internal instruction memory (default 16kb)62131 0720
MTIMEMachine system timer27416600
NCONumerically-controlled oscillator25422600
PWMPulse-width modulation controller716900
SPISerial peripheral interface13812400
SYSINFOSystem configuration information memory111000
TRNGTrue random number generator13210500
TWITwo-wire interface774600
UART0/1Universal asynchronous receiver/transmitter 0/117613200
WDTWatchdog timer604500
WISHBONEExternal memory interface12910400

NEORV32 Processor - Exemplary FPGA Setups

Exemplary processor implementation results for different FPGA platforms. The processor setup uses the default peripheral configuration (like no CFS and no TRNG), no external memory interface and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the processor's top entity signals to FPGA pins - except for the Wishbone bus and the interrupt signals. The "default" strategy of each toolchain is used.

Results generated for hardware version

VendorFPGABoardToolchainCPU ConfigurationLUT / LEFF / REGDSPMemory BitsBRAM / EBRSPRAMFrequency
IntelCyclone IV EP4CE22F17C6NTerasic DE0-NanoQuartus Prime Lite 20.1rv32imc + u + Zicsr + Zifencei3813 (17%)1904 (8%)0 (0%)231424 (38%)--119 MHz
LatticeiCE40 UltraPlus iCE40UP5K-SG48IUpduino v2.0Radiant 2.1 (Synplify Pro)rv32ic + u + Zicsr + Zifencei4397 (83%)1679 (31%)0 (0%)-12 (40%)4 (100%)c 22.15 MHz
XilinxArtix-7 XC7A35TICSG324-1LArty A7-35TVivado 2019.2rv32imc + u + Zicsr + Zifencei + PMP2465 (12%)1912 (5%)0 (0%)-8 (16%)-c 100 MHz


  • The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DMEM (each 64kb). The FPGA-specific memory components can be found in rtl/fpga_specific.
  • The clock frequencies marked with a "c" are constrained clocks. The remaining ones are f_max results from the place and route timing reports.
  • The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32 bootloader to store and automatically boot an application program after reset (both tested successfully).
  • The setups with PMP implement 2 regions with a minimal granularity of 64kB.
  • No HPM counters are implemented.


CoreMark Benchmark

The CoreMark CPU benchmark was executed on the NEORV32 and is available in the sw/example/coremark project folder. This benchmark tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.

Hardware:       32kB IMEM, 16kB DMEM, no caches, 100MHz clock
CoreMark:       2000 iterations, MEM_METHOD is MEM_STACK
Compiler:       RISCV32-GCC 10.1.0 (rv32i toolchain)
Compiler flags: default, see makefile
Peripherals:    UART for printing the results

Results generated for hardware version

CPU (including Zicsr)Executable SizeOptimizationCoreMark ScoreCoreMarks/MHz
rv32i28 756 bytes-O336.360.3636
rv32im27 516 bytes-O368.970.6897
rv32imc22 008 bytes-O368.970.6897
rv32imc + FAST_MUL_EN22 008 bytes-O386.960.8696
rv32imc + FAST_MUL_EN + FAST_SHIFT_EN22 008 bytes-O390.910.9091

The FAST_MUL_EN configuration uses DSPs for the multiplier of the M extension (enabled via the FAST_MUL_EN generic). The FAST_SHIFT_EN configuration uses a barrel shifter for CPU shift operations (enabled via the FAST_SHIFT_EN generic).

When the C extension is enabled, branches to an unaligned uncompressed instruction require additional instruction fetch cycles.

Instruction Cycles

The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence, each instruction requires several clock cycles to execute (2 cycles for ALU operations, ..., 40 cycles for divisions). The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available CPU extensions. By default the CPU-internal shifter (e.g. for the SLL instruction) as well as the multiplier and divider of the M extension use a bit-serial approach and require several cycles for completion.

The following table shows the performance results for successfully running 2000 CoreMark iterations, which reflects a pretty good "real-life" work load. The average CPI is computed by dividing the total number of required clock cycles (only the timed core to avoid distortion due to IO wait cycles; sampled via the cycle[h] CSRs) by the number of executed instructions (instret[h] CSRs). The executables were generated using optimization -O3.

Results generated for hardware version

CPU (including Zicsr)Required Clock CyclesExecuted InstructionsAverage CPI
rv32i5 595 750 5031 466 028 6073.82
rv32im2 966 086 503598 651 1434.95
rv32imc2 981 786 734611 814 9184.87
rv32imc + FAST_MUL_EN2 399 234 734611 814 9183.92
rv32imc + FAST_MUL_EN + FAST_SHIFT_EN2 265 135 174611 814 9483.70

The FAST_MUL_EN configuration uses DSPs for the multiplier of the M extension (enabled via the FAST_MUL_EN generic). The FAST_SHIFT_EN configuration uses a barrel shifter for CPU shift operations (enabled via the FAST_SHIFT_EN generic).

When the C extension is enabled branches to an unaligned uncompressed instruction require additional instruction fetch cycles.

Top Entities

The top entity of the NEORV32 Processor (SoC) is rtl/core/neorv32_top.vhd, which provides a Wishbone b4-compatoible bus interface.

:information_source: It is recommended to use the processor setup even if you want to use the CPU in stand-alone mode. Simply disable all the processor-internal modules via the generics and you will get a "CPU wrapper" that already provides a minimal CPU environment and an external memory interface (like AXI4). This setup also allows to further use the default bootloader and software framework. From this base you can start building your own processor system.

Use the top's generics to configure the system according to your needs. Each generic is initilized with the default configuration. Detailed information regarding the interface signals and configuration generics can be found in the :page_facing_up: NEORV32 data sheet (pdf).

All signals of the top entity are of type std_ulogic or std_ulogic_vector, respectively (except for the processor's TWI signals, which are of type std_logic). Leave all unused output ports unconnected and tie all unused input ports to zero.

Alternative top entities, like the simplified "hello world" test setup or CPU/Processor wrappers with resolved port signal types (i.e. std_logic), can be found in rtl/top_templates.

AXI4 Connectivity

Via the rtl/top_templates/neorv32_top_axi4lite.vhd wrapper the NEORV32 provides an AXI4-Lite compatible master interface. This wrapper instantiates the default NEORV32 processor top entitiy and implements a Wishbone to AXI4-Lite bridge.

The AXI4-Lite interface has been tested using Xilinx Vivado 19.2 block designer:


The processor was packed as custom IP using neorv32_top_axi4lite.vhd as top entity. The AXI interface is automatically detected by the packager. All remaining IO interfaces are available as custom signals. The configuration generics are available via the "customize IP" dialog. In the figure above the resulting IP block is named "neorv32_top_axi4lite_v1_0". (Note: Use Syntheiss option "global" when generating the block design to maintain the internal TWI tri-state drivers.)

The setup uses an AXI interconnect to attach two block RAMs to the processor. Since the processor in this example is configured without IMEM and DMEM, the attached block RAMs are used for storing instructions and data: the first RAM is used as instruction memory and is mapped to address 0x00000000 - 0x00003fff (16kB), the second RAM is used as data memory and is mapped to address 0x80000000 - 0x80001fff (8kB).

Getting Started

This overview is just a short excerpt from the Let's Get It Started section of the NEORV32 documentary:

:page_facing_up: NEORV32 data sheet

1. Get the Toolchain

At first you need a RISC-V GCC toolchain. You can either download the sources and build the toolchain by yourself, or you can download a prebuilt one and install it.

To build the toolchain by yourself, follow the official build instructions. Make sure to use the ilp32 or ilp32e ABI.

Alternatively, you can download a prebuilt toolchain. I have uploaded the toolchains I am using to GitHub. These toolchains were compiled on a 64-bit x86 Ubuntu 20.04 LTS (Ubuntu on Windows, actually). Download the toolchain of choice: :octocat:

You can also use the toolchains provided by SiFive. These are 64-bit toolchains that can also emit 32-bit RISC-V code. They were compiled for more sophisticated machines (rv32imac) so make sure the according NEORV32 hardware extensions are enabled.

:warning: Keep in mind that – for instance – a rv32imc toolchain only provides library code compiled with compressed and mul/div instructions! Hence, this code cannot be executed (without emulation) on an architecture without these extensions!

To check everything works fine, make sure GNU Make and a native GCC compiler are installed. Test the installation of the RISC-V toolchain by navigating to an example program project like sw/example/blink_led and running:

neorv32/sw/example/blink_led$ make check

2. Download the NEORV32 Project

Get the sources of the NEORV32 Processor project. The simplest way is using git clone (suggested for easy project updates via git pull):

$ git clone

Alternatively, you can either download a specific release or get the most recent version of this project as *.zip file.

3. Create a new FPGA Project

Create a new project with your FPGA design tool of choice. Add all the *.vhd files from the rtl/core folder to this project. Make sure to add these files to a new design library called neorv32.

You can either instantiate the processor's top entity or one of its wrappers in your own project. If you just want to try thing out, you can use the simple test setup (rtl/top_templates/neorv32_test_setup.vhd) as top entity.

neorv32 test setup

This test setup instantiates the processor and implements most of the peripherals and some ISA extensions. Only the UART0 communications lines, clock, reset and some GPIO output signals are propagated as actual top entity interface signals. Basically, it is a FPGA version of a "hello world" example:

  entity neorv32_test_setup is
    port (
      -- Global control --
      clk_i       : in  std_ulogic := '0'; -- global clock, rising edge
      rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async
      -- GPIO --
      gpio_o      : out std_ulogic_vector(7 downto 0); -- parallel output
      -- UART0 --
      uart0_txd_o : out std_ulogic;       -- UART0 send data
      uart0_rxd_i : in  std_ulogic := '0' -- UART0 receive data
  end neorv32_test_setup;

4. Compile an Example Program

The NEORV32 project includes several example program project from which you can start your own application. There are example programs to check out the processor's peripheral like I2C or the true-random number generator. And yes, there is also a port of Conway's Game of Life available! :wink:

Simply compile one of these projects using

neorv32/sw/example/blink_led$ make clean_all exe

This will create a NEORV32 executable neorv32_exe.bin in the same folder, which you can upload via the bootloader.

5. Upload the Executable via the Bootloader

Connect your FPGA board via UART to your computer and open the according port to interface with the fancy NEORV32 bootloader. The bootloader uses the following default UART configuration:

  • 19200 Baud
  • 8 data bits
  • 1 stop bit
  • No parity bits
  • No transmission / flow control protocol (raw bytes only)
  • Newline on \r\n (carriage return & newline) - also for sent data

Use the bootloader console to upload the neorv32_exe.bin executable gerated during application compiling and run your application.

<< NEORV32 Bootloader >>

BLDV: Nov  7 2020
HWV:  0x01040606
CLK:  0x0134FD90 Hz
USER: 0x0001CE40
MISA: 0x42801104
PROC: 0x03FF0035
IMEM: 0x00010000 bytes @ 0x00000000
DMEM: 0x00010000 bytes @ 0x80000000

Autoboot in 8s. Press key to abort.

Available CMDs:
 h: Help
 r: Restart
 u: Upload
 s: Store to flash
 l: Load from flash
 e: Execute
CMD:> u
Awaiting neorv32_exe.bin... OK
CMD:> e

Blinking LED demo program

Going further: Take a look at the Let's Get It Started! chapter of the :page_facing_up: NEORV32 data sheet.


I'm always thankful for help! So if you have any questions, bug reports, ideas or if you want to give any kind of feedback, feel free to open a new issue, start a new discussion on GitHub or directly drop me a line.

Here is a simple guide line if you'd like to contribute to this repository:

  1. :star: this repository :wink:
  2. Check out the project's code of conduct
  3. Fork this repository and clone the fork
  4. Create a feature branch in your fork: git checkout -b awesome_new_feature_branch
  5. Create a new remote for the upstream repo: git remote add upstream
  6. Commit your modifications: git commit -m "Awesome new feature!"
  7. Push to the branch: git push origin awesome_new_feature_branch
  8. Create a new pull request

This project is released under the BSD 3-Clause license. No copyright infringement intended. Other implied or used projects might have different licensing - see their documentation to get more information.


If you are using the NEORV32 or parts of the project in some kind of publication, please cite it as follows:

S. Nolting, "The NEORV32 RISC-V Processor",

BSD 3-Clause License

Copyright (c) 2021, Stephan Nolting. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.


Our website contains links to the websites of third parties ("external links"). As the content of these websites is not under our control, we cannot assume any liability for such external content. In all cases, the provider of information of the linked websites is liable for the content and accuracy of the information provided. At the point in time when the links were placed, no infringements of the law were recognisable to us. As soon as an infringement of the law becomes known to us, we will immediately remove the link in question.

Proprietary Notice

"Artix" and "Vivado" are trademarks of Xilinx Inc.

"Cyclone" and "Quartus Prime Lite" are trademarks of Intel Corporation.

"iCE40", "UltraPlus" and "Radiant" are trademarks of Lattice Semiconductor Corporation.

"AXI", "AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.



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