The NEORV32 Processor (RISC-V)

Project maintainers


Name: neorv32
Created: Jun 23, 2020
Updated: Jul 20, 2020
SVN Updated: Jul 4, 2021
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 1 solved
Star8you like it: star it!

Other project properties

Development status:Stable
Additional info:Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: B.4
License: BSD

GitHub Pages Documentation

riscv-arch-test Processor Implementation Windows


The NEORV32 RISC-V Processor

license release datasheet (pdf) datasheet (html) userguide (pdf) userguide (html) doxygen


neorv32 Overview

The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom / customizable microcontroller.

:information_source: Want to know more? Check out the project's rationale.

:books: For detailed information take a look at the NEORV32 documentation (online at GitHub-pages). The doxygen-based documentation of the software framework is also available online at GitHub-pages.

:label: The project's change log is available in To see the changes between official releases visit the project's release page.

:package: The setups folder provides exemplary setups targeting various FPGA boards and toolchains to get you started.

:spiral_notepad: Check out the project boards for a list of current ideas, TODOs, features being planned and work-in-progress.

:bulb: Feel free to open a new issue or start a new discussion if you have questions, comments, ideas or bug-fixes. Check out how to contribute in

:rocket: Check out the quick links below or directly jump to the User Guide to get started setting up your NEORV32 setup!

Project Key Features

  • CPU plus Processor/SoC plus Software Framework & Tooling
  • completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
  • fully synchronous design, no latches, no gated clocks
  • be as small as possible (while being as RISC-V-compliant as possible) – but with a reasonable size-performance trade-off (the processor has to fit in a Lattice iCE40 UltraPlus 5k low-power FPGA running at 22+ MHz)
  • from zero to printf("hello world!"); - completely open source and documented
  • easy to use even for FPGA/RISC-V starters – intended to work out of the box

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NEORV32 Processor Features

The NEORV32 Processor (top entity: rtl/core/neorv32_top.vhd) provides a full-featured SoC build around the NEORV32 CPU. It is highly configurable via generics to allow a flexible customization according to your needs. Note that all modules listed below are optional. In-depth detailed information regarding the processor/SoC can be found in the :books: online documentation - "NEORV32 Processors (SoC)".


  • processor-internal data and instruction memories (DMEM / IMEM) & cache (iCACHE)
  • bootloader (BOOTLDROM) with serial user interface
    • supports boot via UART or from external SPI flash


  • machine system timer (MTIME), RISC-V spec. compatible
  • watchdog timer (WDT)


SoC Connectivity and Integration

  • 32-bit external bus interface, Wishbone b4 compatible (WISHBONE)
    • wrapper for AXI4-Lite master interface
  • 32-bit stram link interface with up to 8 independent RX and TX links (SLINK)
    • AXI4-Stream compatible
  • external interrupt controller with up to 32 channels (XIRQ)
  • alternative top entities/wrappers providing simplified and/or resolved top entity ports for easy system integration
  • custom functions subsystem (CFS) for tightly-coupled custom co-processor extensions


:information_source: It is recommended to use the processor setup even if you want to use the CPU in stand-alone mode. Just disable all optional processor-internal modules via the according generics and you will get a "CPU wrapper" that provides a minimal CPU environment and an external memory interface (like AXI4). This minimal setup allows to further use the default bootloader and software framework. From this base you can start building your own processor system.

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FPGA Implementation Results - Processor

The hardware resources used by a specifc processor setup is defined by the implemented CPU extensions (see below), the configuration of the peripheral modules and some "glue logic". Section "Processor Modules" of the online datasheet shows the ressource utilization of each optional processor module to estimate the actual setup's hardware requirements.

:information_source: The setups folder provides exemplary FPGA setups targeting various FPGA boards and toolchains. These setups also provide ressource utilization reports for different SoC configurations

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NEORV32 CPU Features

:books: In-depth detailed information regarding the CPU can be found in the online documentation - "NEORV32 Central Processing Unit".

The CPU (top entity: rtl/core/neorv32_cpu.vhd) implements the RISC-V 32-bit rv32 ISA with optional extensions (see below). It is compatible to a subset of the Unprivileged ISA Specification (Version 2.2) and a subset of the Privileged Architecture Specification (Version 1.12-draft). Compatiility is checked by passing the official RISC-V architecture tests (see riscv-arch-test/README).

The core implements a little-endian von-Neumann architecture using two pipeline stages. Each stage uses a multi-cycle processing scheme. The CPU supports three privilege levels (machine and optional user and debug_mode), three standard RISC-V machine interrupts (MTI, MEI, MSI), a single non-maskable interrupt plus 16 fast interrupt requests as custom extensions. It also supports all standard RISC-V exceptions (instruction/load/store misaligned address & bus access fault, illegal instruction, breakpoint, environment call). As a special "execution safety" extension, all invalid, reserved or malformed instructions will raise an exception.

Available ISA Extensions

Currently, the following optional RISC-V-compatible ISA extensions are implemented (linked to the according documentation section). Note that the X extension is always enabled.

RV32 [I/ E] [A] [C] [M] [U] [X] [Zfinx] [Zicsr] [Zifencei] [Zmmul] [PMP] [HPM]

:information_source: The B ISA extension has been temporarily removed from the processor. See B ISA Extension project board.

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FPGA Implementation Results - CPU

:books: More details regarding exemplary FPGA setups including a list of resource utilization by each SoC module can be found in the online documentation - "FPGA Implementation Results".

Implementation results for exemplary CPU configuration generated for an Intel Cyclone IV EP4CE22F17C6N FPGA using Intel Quartus Prime Lite 20.1 ("balanced implementation"). The timing information is derived from the Timing Analyzer / Slow 1200mV 0C Model. No constraints were used at all.

Results generated for hardware version

CPU ConfigurationLEsFFsMemory bitsDSPs (9-bit)f_max
rv32i98040910240125 MHz
rv32i + Zicsr183585610240125 MHz
rv32imac + Zicsr2685115610240125 MHz
rv32imac + Zicsr + u + Zifencei + Zfinx4004181210247118 MHz

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The NEORV32 CPU is based on a two-stages pipelined architecutre. Since both stage use a multi-cycle processing scheme, each instruction requires several clock cycles to execute (2 cycles for ALU operations, up to 40 cycles for divisions). The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available CPU extensions.

The following table shows the performance results(relative CoreMark score and average cycles per instruction) for successfully running 2000 iterations of the CoreMark CPU benchmark. The source files are available in sw/example/coremark.

**CoreMark Setup**
Hardware:       32kB IMEM, 8kB DMEM, no caches, 100MHz clock
CoreMark:       2000 iterations, MEM_METHOD is MEM_STACK
Compiler:       RISCV32-GCC 10.1.0 (rv32i toolchain)
Compiler flags: default, see makefile; optimization -O3

Results generated for hardware version

CPU (including Zicsr extension)Executable SizeCoreMark ScoreCoreMarks/MHzTotal Clock CyclesExecuted InstructionsAverage CPI
rv32i28 756 bytes36.360.3636559575050314660286073.82
rv32imc22 008 bytes68.970.689729817867346118149184.87
rv32imc + FAST_MUL_EN + FAST_SHIFT_EN22 008 bytes90.910.909122651351746118149483.70

:information_source: The FAST_MUL_EN configuration uses DSPs for the multiplier of the M extension. The FAST_SHIFT_EN configuration uses a barrel shifter for CPU shift operations.

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Software Framework and Tooling

:books: In-depth detailed information regarding the software framework can be found in the online documentation - "Software Framework".

  • core libraries for high-level usage of the provided functions and peripherals
  • application compilation based on GNU makefiles
  • gcc-based toolchain (pre-compiled toolchains available)
  • bootloader with UART interface console
  • runtime environment for handling traps
  • several example programs to get started including CoreMark, FreeRTOS and Conway's Game of Life
  • doxygen-based documentation, available on GitHub pages
  • supports implementation using open source tooling (GHDL, Yosys and nextpnr; in the future Verilog-to-Routing); both, software and hardware can be developed and debugged with open source tooling
  • continuous Integration is available for:
    • allowing users to see the expected execution/output of the tools
    • ensuring specification compliance
    • catching regressions
    • providing ready-to-use and up-to-date bitstreams and documentation

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Getting Started

This overview provides some quick links to the most important sections of the online Data Sheet and the online User Guide.

:electric_plug: Hardware Overview

:floppy_disk: Software Overview

:rocket: User Guides (see full User Guide)

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A big shoutout to all contributors, who helped improving this project! :heart:

RISC-V - Instruction Sets Want To Be Free!

Continous integration provided by :octocat: GitHub Actions and powered by GHDL.

Made with :coffee: in Hannover, Germany :eu: