OpenCores

The NEORV32 Processor (RISC-V)

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Details

Name: neorv32
Created: Jun 23, 2020
Updated: Jul 20, 2020
SVN Updated: Nov 26, 2021
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 1 solved
Star10you like it: star it!

Other project properties

Category:Processor
Language:VHDL
Development status:Stable
Additional info:Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: B.4
License: BSD

GitHub Pages Documentation \ riscv-arch-test Processor Implementation Windows

NEORV32

The NEORV32 RISC-V Processor

license release DOI \ datasheet (pdf) datasheet (html) userguide (pdf) userguide (html) doxygen Gitter

  1. Overview
    1. Key Features
  2. Processor/SoC Features
    1. FPGA Implementation Results
  3. CPU Features
    1. Available ISA Extensions
    2. FPGA Implementation Results
    3. Performance
  4. Software Framework & Tooling
  5. Getting Started :rocket:

1. Overview

neorv32 Overview

The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom / customizable microcontroller.

Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. Whenever an unexpected situation occurs, the application code is informed via hardware exceptions.

:thinking: Want to know more? Check out the project's rationale.

:books: For detailed information take a look at the NEORV32 documentation (online at GitHub-pages). The doxygen-based documentation of the software framework is also available online at GitHub-pages.

:label: The project's change log is available in CHANGELOG.md. To see the changes between official releases visit the project's release page.

:package: The setups folder provides exemplary setups targeting various FPGA boards and toolchains to get you started. Several example programs (including a FreeRTOS port) to be run on your setup can be found in sw/example.

:kite: Supported by upstream Zephyr OS.

:bulb: Feel free to open a new issue or start a new discussion if you have questions, comments, ideas or if something is not working as expected. Or have a chat on our gitter channel.

:rocket: Check out the quick links below or directly jump to the User Guide to get started setting up your NEORV32 setup!

Project Key Features

  • all-in-one: CPU plus SoC plus Software Framework & Tooling
  • completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
  • fully synchronous design, no latches, no gated clocks
  • be as small as possible while being as RISC-V-compliant as possible – but with a reasonable size-performance trade-off: the processor (CPU including privileged architecture) fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz
  • from zero to printf("hello world!"); - completely open source and documented
  • easy to use even for FPGA/RISC-V starters – intended to work out of the box

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2. NEORV32 Processor Features

The NEORV32 Processor (top entity: rtl/core/neorv32_top.vhd) provides a full-featured SoC build around the NEORV32 CPU. It is highly configurable via generics to allow a flexible customization according to your needs. Note that all modules listed below are optional.

Memory

  • processor-internal data and instruction memories (DMEM / IMEM) & cache (iCACHE)
  • bootloader (BOOTLDROM) with serial user interface
    • allows booting application code via UART or from external SPI flash

Timers

  • machine system timer, 64-bit (MTIME), RISC-V spec. compatible
  • general purpose 32-bit timer (GPTMR)
  • watchdog timer (WDT)

IO

SoC Connectivity and Integration

  • 32-bit external bus interface, Wishbone b4 compatible (WISHBONE)
    • wrapper for AXI4-Lite master interface
    • wrapper for Avalon-MM master interface
  • 32-bit stream link interface with up to 8 independent RX and TX links (SLINK)
    • AXI4-Stream compatible
  • external interrupt controller with up to 32 channels (XIRQ)
  • custom functions subsystem (CFS) for tightly-coupled custom co-processor extensions

Advanced

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FPGA Implementation Results - Processor

The hardware resources used by a specific processor setup is defined by the implemented CPU extensions, the configuration of the peripheral modules and some "glue logic". Section FPGA Implementation Results - Processor Modules of the online datasheet shows the resource utilization of each optional processor module to allow an estimation of the actual setup's hardware requirements.

:information_source: The setups folder provides exemplary FPGA setups targeting various FPGA boards and toolchains. These setups also provide resource utilization reports for different SoC configurations

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3. NEORV32 CPU Features

The CPU (top entity: rtl/core/neorv32_cpu.vhd) implements the RISC-V 32-bit rv32 ISA with optional extensions (see below). It is compatible to subsets of the Unprivileged ISA Specification (Version 2.2) and the Privileged Architecture Specification (Version 1.12-draft). Compatibility is checked by passing the official RISC-V architecture tests (see sim/README).

The core is a little-endian Von-Neumann machine implemented as multi-cycle architecture. However, the CPU's front end (instruction fetch) and back end (instruction execution) can work independently to increase performance. Currently, three privilege levels (machine and optional user and debug_mode) are supported. The CPU implements all three standard RISC-V machine interrupts (MTI, MEI, MSI) plus 16 fast interrupt requests as custom extensions. It also supports all standard RISC-V exceptions (instruction/load/store misaligned address & bus access fault, illegal instruction, breakpoint, environment calls).

:books: In-depth detailed information regarding the CPU can be found in the Data Sheet: NEORV32 Central Processing Unit.

Available ISA Extensions

Currently, the following optional RISC-V-compatible ISA extensions are implemented (linked to the according documentation section). Note that the X extension is always enabled.

RV32 [I/ E] [A] [B] [C] [M] [U] [X] [Zfinx] [Zicsr] [Zicntr] [Zihpm] [Zifencei] [Zmmul] [PMP] [DEBUG]

:warning: The B, Zfinx and Zmmul RISC-V extensions are frozen but not officially ratified yet. Hence, there is no upstream gcc support. To circumvent this, the NEORV32 software framework provides intrinsic libraries for these extensions.

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FPGA Implementation Results - CPU

Implementation results for exemplary CPU configuration generated for an Intel Cyclone IV EP4CE22F17C6N FPGA using Intel Quartus Prime Lite 20.1 ("balanced implementation"). The timing information is derived from the Timing Analyzer / Slow 1200mV 0C Model. No constraints were used at all.

Results generated for hardware version 1.5.7.10.

CPU ConfigurationLEsFFsMemory bitsDSPs (9-bit)f_max
rv32i80635910240125 MHz
rv32i_Zicsr_Zicntr172981310240124 MHz
rv32imac_Zicsr_Zicntr2511107410240124 MHz

:informationsource: An incremental list of CPU extension's hardware utilization can found in the [_Data Sheet: FPGA Implementation Results - CPU](https://stnolting.github.io/neorv32/#_cpu).

:informationsource: The CPU (and also the SoC) provides advanced options to optimize for performance, area or energy. See [_User Guide: Application-Specific Processor Configuration](https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration) for more information.

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Performance

The NEORV32 CPU is based on a two-stages pipelined architecture. Since both stage use a multi-cycle processing scheme, each instruction requires several clock cycles to execute (2 cycles for ALU operations, up to 40 cycles for divisions). The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available CPU extensions.

The following table shows the performance results (relative CoreMark score and average cycles per instruction) for exemplary CPU configuration running 2000 iterations of the CoreMark CPU benchmark. The source files are available in sw/example/coremark. A simple(!) port of the Dhrystone benchmark is also available in sw/example/dhrystone.

Results generated for hardware version 1.5.7.10.

CPU ConfigurationCoreMark ScoreCoreMarks/MHzAverage CPI
small (rv32i_Zicsr)33.890.33894.04
medium (rv32imc_Zicsr)62.500.62505.34
performance (rv32imc_Zicsr + perf. options)95.230.95233.54

:informationsource: More information regarding the CPU performance can be found in the [_Data Sheet: CPU Performance](https://stnolting.github.io/neorv32/#_cpu_performance).

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4. Software Framework and Tooling

:books: In-depth detailed information regarding the software framework can be found in the Data Sheet: Software Framework.

  • core libraries for high-level usage of the provided functions and peripherals
  • application compilation based on GNU makefiles
  • gcc-based toolchain (pre-compiled toolchains available)
  • bootloader with UART interface console
  • runtime environment for handling traps
  • several example programs to get started including CoreMark, FreeRTOS and Conway's Game of Life
  • doxygen-based documentation, available on :books: GitHub pages
  • supports implementation using open source tooling (GHDL, Yosys and nextpnr; in the future Verilog-to-Routing); both, software and hardware can be developed and debugged with open source tooling
  • continuous integration :octocat: is available for:
    • allowing users to see the expected execution/output of the tools
    • ensuring specification compliance
    • catching regressions
    • providing ready-to-use and up-to-date bitstreams and documentation

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5. Getting Started

This overview provides some quick links to the most important sections of the online Data Sheet and the online User Guide.

:electric_plug: Hardware Overview

:floppy_disk: Software Overview

:rocket: User Guide

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Acknowledgements

A big shout-out to the community and all contributors, who helped improving this project! :heart:

RISC-V - Instruction Sets Want To Be Free!

Continuous integration provided by :octocat: GitHub Actions and powered by GHDL.