The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom / customizable microcontroller.
:information_source: Want to know more? Check out the project's rationale.
:spiral_notepad: Check out the project boards for a list of current ideas, TODOs, features being planned and work-in-progress.
printf("hello world!");- completely open source and documented
The NEORV32 Processor (top entity:
provides a full-featured SoC build around the NEORV32 CPU. It is highly configurable via generics
to allow a flexible customization according to your needs. Note that all modules listed below are optional.
In-depth detailed information regarding the processor/SoC can be found in the :books:
online documentation - "NEORV32 Processors (SoC)".
SoC Connectivity and Integration
:information_source: It is recommended to use the processor setup even if you want to use the CPU in stand-alone mode. Just disable all optional processor-internal modules via the according generics and you will get a "CPU wrapper" that provides a minimal CPU environment and an external memory interface (like AXI4). This minimal setup allows to further use the default bootloader and software framework. From this base you can start building your own processor system.
The hardware resources used by a specifc processor setup is defined by the implemented CPU extensions (see below), the configuration of the peripheral modules and some "glue logic". Section "FPGA Implementation Results - Processor Modules" of the online datasheet shows the ressource utilization of each optional processor module to allow an estimation of the actual setup's hardware requirements.
setups folder provides exemplary FPGA
setups targeting various FPGA boards and toolchains. These setups also provide ressource utilization reports for different
:books: In-depth detailed information regarding the CPU can be found in the online documentation - "NEORV32 Central Processing Unit".
The CPU (top entity:
implements the RISC-V 32-bit
rv32 ISA with optional extensions (see below). It is compatible to a subset of the
Unprivileged ISA Specification (Version 2.2)
and a subset of the Privileged Architecture Specification (Version 1.12-draft).
Compatiility is checked by passing the official RISC-V architecture tests
The core implements a little-endian von-Neumann architecture using two pipeline stages. Each stage uses a multi-cycle processing
scheme. The CPU supports three privilege levels (
machine and optional
debug_mode), three standard RISC-V machine
MSI), a single non-maskable interrupt plus 16 fast interrupt requests as custom extensions.
It also supports all standard RISC-V exceptions (instruction/load/store misaligned address & bus access fault, illegal
instruction, breakpoint, environment call)
(see :books: "Full Virtualization").
Currently, the following optional RISC-V-compatible ISA extensions are implemented (linked to the according
documentation section). Note that the
X extension is always enabled.
Zmmul RISC-V extensions are frozen but not officially ratified yet. Hence, there is no
upstream gcc support. To circumvence this, the NEORV32 software framework provides intrinsic libraries for these extensions.
Implementation results for exemplary CPU configuration generated for an Intel Cyclone IV EP4CE22F17C6N FPGA using Intel Quartus Prime Lite 20.1 ("balanced implementation"). The timing information is derived from the Timing Analyzer / Slow 1200mV 0C Model. No constraints were used at all.
Results generated for hardware version
|CPU Configuration||LEs||FFs||Memory bits||DSPs (9-bit)||f_max|
:informationsource: An incremental list of CPU exntension's hardware utilization can found in [online documentation - "FPGA Implementation Results - CPU"_](https://stnolting.github.io/neorv32/#_cpu).
:information_source: The CPU provides options to further reduce the footprint (for example by constraining the CPU-internal counters). See the online data sheet for more information.
The NEORV32 CPU is based on a two-stages pipelined architecutre. Since both stage use a multi-cycle processing scheme, each instruction requires several clock cycles to execute (2 cycles for ALU operations, up to 40 cycles for divisions). The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available CPU extensions.
The following table shows the performance results (relative CoreMark score and average cycles per instruction) for
exemplary CPU configuration running 2000 iterations of the CoreMark CPU benchmark.
The source files are available in
:informationsource: A _simple port of the Dhrystone benchmark is also available:
**CoreMark Setup** Hardware: 32kB IMEM, 8kB DMEM, no caches, 100MHz clock CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain) Compiler flags: default, see makefile; optimization -O3
Results generated for hardware version
|CPU Configuration||CoreMark Score||CoreMarks/MHz||Average CPI|
:informationsource: More information regarding the CPU performance can be found in the [online documentation - "CPU Performance"_](https://stnolting.github.io/neorv32/#_cpu_performance).
:books: In-depth detailed information regarding the software framework can be found in the online documentation - "Software Framework".
doxygen-based documentation, available on GitHub pages
Rationale - NEORV32: why, how come, what for
NEORV32 Processor - the SoC
NEORV32 CPU - the CPU
A big shoutout to all contributors, who helped improving this project! :heart:
RISC-V - Instruction Sets Want To Be Free!
Made with :coffee: in Hannover, Germany :eu: