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Name: primal_origins_soc
Created: Jan 13, 2026
Updated: Jan 16, 2026
SVN Updated: Jan 17, 2026
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star1you like it: star it!

Other project properties

Category:System on Chip
Language:Verilog
Development status:Beta
Additional info:Design done, Specification done
WishBone compliant: No
WishBone version: n/a
License: CERN-OHL-S
<p align="center"> <img src="docs/images/system_architecture.svg" alt="Primal Origins Architecture" width="600"> </p><h1 align="center">Primal Origins: Omega</h1> <h3 align="center">Hardware-Enforced Economic Policy • Silicon IP Core</h3><p align="center"> <i>"What is needed is an economic system based not on trust, but on cryptographic proof enforced by silicon—allowing any two parties to transact under rules that cannot be changed by anyone, including the system's creators."</i> </p><p align="center"> <a href="https://ci.codeberg.org/ErickAlexander/Primal-Origins-SoC-IP-Core"><img src="https://ci.codeberg.org/api/badges/ErickAlexander/Primal-Origins-SoC-IP-Core/status.svg" alt="CI"></a> <a href="evidence/"><img src="https://img.shields.io/badge/Tests-1.7M%2B_Passed-00C853?style=flat-square" alt="Tests"></a> <a href="verification/formal/"><img src="https://img.shields.io/badge/Formal-SMT_Proven-2962FF?style=flat-square" alt="Formal"></a> <a href="LICENSE"><img src="https://img.shields.io/badge/License-CERN--OHL--S_v2-FF6D00?style=flat-square" alt="License"></a> <a href="https://opencores.org/projects/primal_origins_soc"><img src="https://img.shields.io/badge/OpenCores-Listed-8B0000?style=flat-square" alt="OpenCores"></a> </p><p align="center"> <a href="#quick-start">Quick Start</a> • <a href="#the-problem">Problem</a> • <a href="#the-solution">Solution</a> • <a href="#verification">Verification</a> • <a href="#specifications">Specs</a> • <a href="#get-involved">Contribute</a> </p>

Quick Start

# Clone
git clone https://codeberg.org/ErickAlexander/Primal-Origins-SoC-IP-Core.git
cd Primal-Origins-SoC-IP-Core

# Verify (1.7M+ tests in Docker)
docker build -t primal-verify . && docker run --rm primal-verify

# Or run directly
pip install hypothesis numpy scipy
python verification/run_all_verification.py

Core RTL: rtl/stack02_hardlaw/smf_unit.sv — The Hard-Law Economic Engine


The Problem

Every financial system has a backdoor.

SystemWho Can Change the Rules
Central BankingMonetary policy committees
Commercial BankingTerms of service updates
CryptocurrencyHard forks, governance votes
Smart ContractsUpgrade proxies, admin keys
Payment NetworksUnilateral fee changes

Software can be patched. Consensus can be bought. Keys can be compromised.

The root cause: economic rules exist as information, which can be copied, modified, and replaced.


The Solution

Encode economic rules as physics.

When you fabricate an integrated circuit, logic gates are physically instantiated in silicon. Changing that logic requires:

  1. Redesigning the circuit
  2. Manufacturing new photomasks ($1-10M)
  3. Fabricating new wafers (3-6 months)
  4. Physically replacing every deployed chip

This is not "code is law." This is physics is law.

╔══════════════════════════════════════════════════════════════╗
║           THE HARD-LAW SPLIT (Metal-Mask Constants)          ║
╠══════════════════════════════════════════════════════════════╣
║                                                              ║
║   Every transaction through this silicon:                    ║
║                                                              ║
║     1.00%  →  Infrastructure Fund                            ║
║     3.00%  →  Liquidity Pool                                 ║
║     2.18%  →  Network Maintenance                            ║
║    93.82%  →  Recipient                                      ║
║   ──────────────────────────────                             ║
║     6.18%  TOTAL (Immutable in Transistors)                  ║
║                                                              ║
║   These percentages are not stored in registers.             ║
║   They are etched in transistors.                            ║
║   Changing them requires new silicon.                        ║
║                                                              ║
╚══════════════════════════════════════════════════════════════╝

Verification

We don't ask you to trust. We ask you to verify.

Test Results

CategoryTestsPass Rate
Mathematical Verification1,020,150100%
Comprehensive Suite765,91299.96%
Total1,786,06299.98%

Formal Verification

MethodToolResult
Bounded Model CheckingSymbiYosys + Z3PROVEN
K-InductionSymbiYosys + Z3PROVEN

Civilization Simulation

MetricResult
Simulated Duration1,000 years
Total Transactions1,999,597
Integrity FailuresZERO
Final StateCivilization thriving

All evidence is public: evidence/ contains logs, VCD waveforms, and reports.


Architecture

┌─────────────────────────────────────────────────────────────────────┐
│                     PRIMAL ORIGINS: OMEGA                           │
│                   11-Stack SoC Architecture                         │
├─────────────────────────────────────────────────────────────────────┤
│                                                                     │
│  ┌─────────┐  ┌─────────┐  ┌─────────┐  ┌─────────┐  ┌─────────┐   │
│  │ STACK01 │  │ STACK02 │  │ STACK03 │  │ STACK05 │  │ STACK06 │   │
│  │   PUF   │  │HARD-LAW │  │BIOLATCH │  │ AES-256 │  │  MESH   │   │
│  │Identity │  │ Engine  │  │Lifecycle│  │ Crypto  │  │   NoC   │   │
│  └────┬────┘  └────┬────┘  └────┬────┘  └────┬────┘  └────┬────┘   │
│       │            │            │            │            │         │
│       └────────────┴────────────┴────────────┴────────────┘         │
│                              │                                      │
│                    ┌─────────┴─────────┐                            │
│                    │   STACK07: PULSE  │                            │
│                    │   Governance Core │                            │
│                    └───────────────────┘                            │
│                                                                     │
│  ┌──────────────────────────────────────────────────────────────┐   │
│  │                     INFRASTRUCTURE                            │   │
│  │   DFT (JTAG/MBIST/LBIST) • SEU Protection • Clock/Reset      │   │
│  └──────────────────────────────────────────────────────────────┘   │
│                                                                     │
└─────────────────────────────────────────────────────────────────────┘

Core Innovation: The Hard-Law Engine (Stack 02) — a 3-stage pipelined arithmetic unit computing the 6.18% split using metal-mask constants. See rtl/stack02_hardlaw/smf_unit.sv.


Specifications

ParameterValue
Target ProcessUniversal — Process-agnostic RTL, portable to any node
IntegrationDrop-in IP block for SoCs, MCUs, FPGAs, ASICs
FrequencyClock-independent (synthesizer determines max frequency)
Latency3 clock cycles per transaction
Throughput1 transaction per 3 clocks (scales with frequency)
Arithmetic128-bit fixed-point
Economic Split6.18% (immutable)
Identity4096-bit SRAM PUF
EncryptionAES-256 (14-round)
Network4×4 mesh NoC, XY routing
RTL Modules31 SystemVerilog files
LicenseCERN-OHL-S v2.0

Portability: Pure synthesizable SystemVerilog with no process-specific primitives. Integrate into any chip — from 180nm legacy nodes to cutting-edge 3nm, FPGAs (Xilinx/Intel), or custom ASICs.


Applications

Use CaseValue Proposition
CBDCsMonetary policy citizens can verify, governments cannot secretly modify
Crypto ExchangesAuditable, tamper-proof fee structures
Creator PlatformsRevenue splits that cannot be changed after the fact
Trade FinanceTrustless escrow without intermediaries
IoT PaymentsMicropayment rails with hardware-guaranteed fees

Status

MilestoneStatus
RTL Design✅ Complete (31 modules)
Verification✅ 1.7M+ tests passing
Formal Proof✅ SMT-proven
1000-Year Simulation✅ Zero failures
Open Synthesis✅ Yosys verified
CI/CD Pipeline✅ Codeberg Woodpecker
FPGA Validation🔄 In progress
Commercial Synthesis⏳ Seeking EDA partner
Silicon Tape-out⏳ Seeking foundry partner

Get Involved

Verify the Design

docker build -t primal-verify . && docker run --rm primal-verify

Read the Core

# The Hard-Law Engine
cat rtl/stack02_hardlaw/smf_unit.sv

# Top-level integration  
cat rtl/top/origin_v_core.sv

Contribute

If You HaveHow You Can Help
TimeReview code, report bugs, improve docs
FPGAValidate on hardware
EDA ToolsRun commercial synthesis
CapitalFund a shuttle run
ConnectionsIntroduce us to foundries

See CONTRIBUTING.md and PARTNERS.md.


Repository Structure

primal-origins-omega/
├── rtl/                      # SystemVerilog source (31 modules)
│   ├── stack02_hardlaw/      # The core: Hard-Law Engine
│   ├── stack05_storage/      # AES-256 encryption
│   ├── stack06_mesh/         # 4×4 NoC
│   └── top/                  # Top-level integration
├── verification/             # 1.7M+ tests
│   ├── standalone/           # Mathematical verification
│   ├── formal/               # SymbiYosys proofs
│   └── cocotb/               # Python testbenches
├── evidence/                 # Execution logs, VCD waveforms
├── docs/                     # Technical documentation
├── synthesis/                # Timing constraints, power intent
├── Dockerfile                # Reproducible environment
└── README.md                 # You are here

Documentation

DocumentDescription
WhitepaperTechnical specification
Architecture ManualAll 11 stacks
Verification EvidenceTest results
VisionWhy we built this
PartnersHow to collaborate

PlatformURL
Codeberg (main)codeberg.org/ErickAlexander/Primal-Origins-SoC-IP-Core
OpenCores (mirror)opencores.org/projects/primal_origins_soc
CI Pipelineci.codeberg.org

License

CERN Open Hardware Licence v2 – Strongly Reciprocal

You may use, modify, and distribute this design. Modifications must be shared under the same license. See LICENSE.


<p align="center"> <br> <b>"Software is promise. Blockchain is consensus. Silicon is physics."</b> <br><br> <img src="https://img.shields.io/badge/Status-Seeking_Partners-blue?style=for-the-badge" alt="Status"> <br><br> <a href="PARTNERS.md"><b>→ Partner With Us ←</b></a> </p>