# Clone
git clone https://codeberg.org/ErickAlexander/Primal-Origins-SoC-IP-Core.git
cd Primal-Origins-SoC-IP-Core
# Verify (1.7M+ tests in Docker)
docker build -t primal-verify . && docker run --rm primal-verify
# Or run directly
pip install hypothesis numpy scipy
python verification/run_all_verification.pyCore RTL: rtl/stack02_hardlaw/smf_unit.sv — The Hard-Law Economic Engine
Every financial system has a backdoor.
| System | Who Can Change the Rules |
|---|---|
| Central Banking | Monetary policy committees |
| Commercial Banking | Terms of service updates |
| Cryptocurrency | Hard forks, governance votes |
| Smart Contracts | Upgrade proxies, admin keys |
| Payment Networks | Unilateral fee changes |
Software can be patched. Consensus can be bought. Keys can be compromised.
The root cause: economic rules exist as information, which can be copied, modified, and replaced.
Encode economic rules as physics.
When you fabricate an integrated circuit, logic gates are physically instantiated in silicon. Changing that logic requires:
This is not "code is law." This is physics is law.
╔══════════════════════════════════════════════════════════════╗
║ THE HARD-LAW SPLIT (Metal-Mask Constants) ║
╠══════════════════════════════════════════════════════════════╣
║ ║
║ Every transaction through this silicon: ║
║ ║
║ 1.00% → Infrastructure Fund ║
║ 3.00% → Liquidity Pool ║
║ 2.18% → Network Maintenance ║
║ 93.82% → Recipient ║
║ ────────────────────────────── ║
║ 6.18% TOTAL (Immutable in Transistors) ║
║ ║
║ These percentages are not stored in registers. ║
║ They are etched in transistors. ║
║ Changing them requires new silicon. ║
║ ║
╚══════════════════════════════════════════════════════════════╝We don't ask you to trust. We ask you to verify.
| Category | Tests | Pass Rate |
|---|---|---|
| Mathematical Verification | 1,020,150 | 100% |
| Comprehensive Suite | 765,912 | 99.96% |
| Total | 1,786,062 | 99.98% |
| Method | Tool | Result |
|---|---|---|
| Bounded Model Checking | SymbiYosys + Z3 | PROVEN |
| K-Induction | SymbiYosys + Z3 | PROVEN |
| Metric | Result |
|---|---|
| Simulated Duration | 1,000 years |
| Total Transactions | 1,999,597 |
| Integrity Failures | ZERO |
| Final State | Civilization thriving |
All evidence is public: evidence/ contains logs, VCD waveforms, and reports.
┌─────────────────────────────────────────────────────────────────────┐
│ PRIMAL ORIGINS: OMEGA │
│ 11-Stack SoC Architecture │
├─────────────────────────────────────────────────────────────────────┤
│ │
│ ┌─────────┐ ┌─────────┐ ┌─────────┐ ┌─────────┐ ┌─────────┐ │
│ │ STACK01 │ │ STACK02 │ │ STACK03 │ │ STACK05 │ │ STACK06 │ │
│ │ PUF │ │HARD-LAW │ │BIOLATCH │ │ AES-256 │ │ MESH │ │
│ │Identity │ │ Engine │ │Lifecycle│ │ Crypto │ │ NoC │ │
│ └────┬────┘ └────┬────┘ └────┬────┘ └────┬────┘ └────┬────┘ │
│ │ │ │ │ │ │
│ └────────────┴────────────┴────────────┴────────────┘ │
│ │ │
│ ┌─────────┴─────────┐ │
│ │ STACK07: PULSE │ │
│ │ Governance Core │ │
│ └───────────────────┘ │
│ │
│ ┌──────────────────────────────────────────────────────────────┐ │
│ │ INFRASTRUCTURE │ │
│ │ DFT (JTAG/MBIST/LBIST) • SEU Protection • Clock/Reset │ │
│ └──────────────────────────────────────────────────────────────┘ │
│ │
└─────────────────────────────────────────────────────────────────────┘Core Innovation: The Hard-Law Engine (Stack 02) — a 3-stage pipelined arithmetic unit computing the 6.18% split using metal-mask constants. See rtl/stack02_hardlaw/smf_unit.sv.
| Parameter | Value |
|---|---|
| Target Process | Universal — Process-agnostic RTL, portable to any node |
| Integration | Drop-in IP block for SoCs, MCUs, FPGAs, ASICs |
| Frequency | Clock-independent (synthesizer determines max frequency) |
| Latency | 3 clock cycles per transaction |
| Throughput | 1 transaction per 3 clocks (scales with frequency) |
| Arithmetic | 128-bit fixed-point |
| Economic Split | 6.18% (immutable) |
| Identity | 4096-bit SRAM PUF |
| Encryption | AES-256 (14-round) |
| Network | 4×4 mesh NoC, XY routing |
| RTL Modules | 31 SystemVerilog files |
| License | CERN-OHL-S v2.0 |
Portability: Pure synthesizable SystemVerilog with no process-specific primitives. Integrate into any chip — from 180nm legacy nodes to cutting-edge 3nm, FPGAs (Xilinx/Intel), or custom ASICs.
| Use Case | Value Proposition |
|---|---|
| CBDCs | Monetary policy citizens can verify, governments cannot secretly modify |
| Crypto Exchanges | Auditable, tamper-proof fee structures |
| Creator Platforms | Revenue splits that cannot be changed after the fact |
| Trade Finance | Trustless escrow without intermediaries |
| IoT Payments | Micropayment rails with hardware-guaranteed fees |
| Milestone | Status |
|---|---|
| RTL Design | ✅ Complete (31 modules) |
| Verification | ✅ 1.7M+ tests passing |
| Formal Proof | ✅ SMT-proven |
| 1000-Year Simulation | ✅ Zero failures |
| Open Synthesis | ✅ Yosys verified |
| CI/CD Pipeline | ✅ Codeberg Woodpecker |
| FPGA Validation | 🔄 In progress |
| Commercial Synthesis | ⏳ Seeking EDA partner |
| Silicon Tape-out | ⏳ Seeking foundry partner |
docker build -t primal-verify . && docker run --rm primal-verify# The Hard-Law Engine
cat rtl/stack02_hardlaw/smf_unit.sv
# Top-level integration
cat rtl/top/origin_v_core.sv| If You Have | How You Can Help |
|---|---|
| Time | Review code, report bugs, improve docs |
| FPGA | Validate on hardware |
| EDA Tools | Run commercial synthesis |
| Capital | Fund a shuttle run |
| Connections | Introduce us to foundries |
See CONTRIBUTING.md and PARTNERS.md.
primal-origins-omega/
├── rtl/ # SystemVerilog source (31 modules)
│ ├── stack02_hardlaw/ # The core: Hard-Law Engine
│ ├── stack05_storage/ # AES-256 encryption
│ ├── stack06_mesh/ # 4×4 NoC
│ └── top/ # Top-level integration
├── verification/ # 1.7M+ tests
│ ├── standalone/ # Mathematical verification
│ ├── formal/ # SymbiYosys proofs
│ └── cocotb/ # Python testbenches
├── evidence/ # Execution logs, VCD waveforms
├── docs/ # Technical documentation
├── synthesis/ # Timing constraints, power intent
├── Dockerfile # Reproducible environment
└── README.md # You are here| Document | Description |
|---|---|
| Whitepaper | Technical specification |
| Architecture Manual | All 11 stacks |
| Verification Evidence | Test results |
| Vision | Why we built this |
| Partners | How to collaborate |
| Platform | URL |
|---|---|
| Codeberg (main) | codeberg.org/ErickAlexander/Primal-Origins-SoC-IP-Core |
| OpenCores (mirror) | opencores.org/projects/primal_origins_soc |
| CI Pipeline | ci.codeberg.org |
CERN Open Hardware Licence v2 – Strongly Reciprocal
You may use, modify, and distribute this design. Modifications must be shared under the same license. See LICENSE.