RC4 Pseudo-random stream generator
Project maintainers
Details
Name: rc4-prbs
Created: May 17, 2012
Updated: Feb 26, 2013
SVN Updated: Jun 2, 2013
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: May 17, 2012
Updated: Feb 26, 2013
SVN Updated: Jun 2, 2013
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star3you like it: star it!
Other project properties
Category:Crypto core
Language:Verilog
Development status:Stable
Additional info:Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Stable
Additional info:Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
RC4 PRBS (Generates the RC4 stream, then you have to XOR it with your data to crypt or decrypt it), takes 768 clocks to do key-expansion, then start outputting one-byte of random stream for every clock (output_read signals valid output in K). Based on RC4 implementation in wikipedia.
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