OpenCores

RV01 RISC-V core :: Overview



Project maintainers

Details

Name: rv01_riscv_core
Created: Dec 11, 2017
Updated: Dec 19, 2017
SVN Updated: Dec 19, 2017
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star1you like it: star it!

Other project properties

Category:Processor
Language:VHDL
Development status:Beta
Additional info:Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

RV01 is a two-way in-order superscalar processor core implementing RISC-V RV32I instruction set with “M” extension according to RISC-V ISA version V2.0, and (with some exception) privileged architecture according to version V1.7. The RV01 core stores instruction and data inside on-chip memory (no cache, no MMU). User-configurable RV01 core features include: instruction/data memory size, scalar/superscalar execution capability, branch/jump prediction, Debug module and PLIC module. "Full-optional" version delivers ~1.8 DMIPS/MHz.
© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.