Tonello, Stefano

RV01 RISC-V core

## Description

RV01 is a two-way in-order superscalar processor core implementing RISC-V RV32I instruction set with “M” extension according to RISC-V ISA version V2.0, and (with some exception) privileged architecture according to version V1.7. The RV01 core stores instruction and data inside on-chip memory (no cache, no MMU). User-configurable RV01 core features include: instruction/data memory size, scalar/superscalar execution capability, branch/jump prediction, Debug module and PLIC module. "Full-optional" version delivers ~1.8 DMIPS/MHz.


<h2 id="description">Description</h2>
<p>RV01 is a two-way in-order superscalar processor core implementing RISC-V RV32I instruction set with “M” extension according to RISC-V ISA version V2.0, and (with some exception) privileged architecture according to version V1.7. The RV01 core stores instruction and data inside on-chip memory (no cache, no MMU). User-configurable RV01 core features include: instruction/data memory size, scalar/superscalar execution capability, branch/jump prediction, Debug module and PLIC module. "Full-optional" version delivers ~1.8 DMIPS/MHz.</p>


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RV01 RISC-V core

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