Description

This module provides SPI Master functionality to your FPGA or ASIC. There are tons of open-source SPI Master implementations. I used them in my projects but needed a module consumes less resources and easier to use with less signal interfaces.

I developed this lw_spi_master module with VHDL language. I published a paper which compares different SPI implementations on FPGAs named as "Design and Implementation of a Lightweight SPI Master IP for Low Cost FPGAs". The paper is unfortunately in Turkish language but abstract is in English and from figures and tables you can understand lots of information, also google translate is another option. The paper is in doc directory.

This module consume 26 FF and 40 LUT in Spartan6 FPGA. Interface signals are only these below:

• clk_i : IN std_logic;
• en_i : IN std_logic;
• mosi_data_i : IN std_logic_vector(7 downto 0);
• miso_data_o : OUT std_logic_vector(7 downto 0);
• data_ready_o : OUT std_logic;
• cs_o : OUT std_logic;
• sclk_o : OUT std_logic;
• mosi_o : OUT std_logic;
• miso_i : IN std_logic

There are only 2 control I/O (en_i, data_ready_o) and 2 data I/O (mosi_data_i, miso_data_o) signals.

The design is FPGA proven, I use this module to communicate ICs and other devices which have SPI slave interface.

The lw_spi_master module consumes little resource but I prefer using spi_master module in my designs because it gives one clock data_ready_o instead more than one in lw_spi_master. So I find it more useful to instantiate in higher level modules. Both files are in rtl directory.

Here simulation waveform for spi_master module:

Here simulation waveform for lw_spi_master module:

The url of the svn repository is: https://opencores.org/websvn/listing/spi_master_lightweight/spi_master_lightweight