SPI Flash controller

Description

This project implements a controller for standard SPI flash ROMs (e.g. ST M25Pxx, Atmel AT25Fxxxx, etc.).
For a design using an (embedded) microcontroller it is often a requirement to store user or configuration information. For this purpose the configuration ROM of the FPGA is a first-choice candidate because it is already there and usually has some space left. By using the VHDL module introduced in this project the microcontroller firmware is greatly simplyfied by moving the complexity of accessing the SPI flash to the hardware.
This core is a spin-off from the "DIY Calculator Hardware" project (URL: http://diycalculator.pcl.at)
and is maintained by Johannes Hausensteiner (johannes.hausensteiner@pcl.at)

Features

The communication to the SPI flash is done through commands which are of different length, with or without parameters, expecting or not responses. The following commands are implemented:
- WREN: Write Enable; before you can write to the flash it is necessary to send this command
- WRDI: Write Disable; does what it says
- RDSR: Read Status Register; the flash chip employs a status register which tells about the chip's state such as write protect, busy, etc.
- WRSR: Write Status Register; write a new value to the status register
- READ: read data; reads an arbitrary number of bytes beginning from a supplied address
- FAST_READ: similar to the READ command, but possibly uses a faster clock
- PP: Page Program; the flash chip is organised in sectors and pages; an arbitrary number of bytes but a maximum of one page size can be written to the flash
- SE: Sector Erase; before data can be programmed into the flash it must be erased. It is only possible to erase sectors as a whole.
- BE: Bulk Erase; erase the whole chip
- RES: Read Signature; each flash chip contains a signature, which is characteristic for the type of chip

The SPI Flash Controller acts as a microprocessor peripheral. Communication is done via several registers:
- Tx data register (write, base plus 0)
- Rx data register (read, base plus 0)
- command register (write, base plus 1)
- status register (read, base plus 1)
- address mid register (write, base plus 2)
- address low register (write, base plus 3)

Note that the address is composed from three bytes. In this implementation the highest byte (= the sector number) is fixed to the topmost sector. Remember that FPGA configuration is stored at the beginning of the flash (starting with address $000000).

For detailed information see the state diagram (SPI_state-diagram.jpg) and the register description (spi-registers.txt) in the doc sub directory of the project in CVS.

Status

- 0.1 25.Sep.2006 JH new, flash sector number is hard coded to 0x0f
- 0.1 21.Nov.2006 JH no changes, submitted to OpenCores.org