Steel is a 3-stage single-issue in-order RISC-V microprocessor core designed to be simple and easy to use. It is intended for use in FPGAs as the processing unit in embedded system designs.
Steel is distributed under the MIT License. See the
Steel documentation (https://rafaelcalcada.github.io/steel-core/) provides information on:
Read the docs carefully before using the core.
To use Steel in your project you must import all files from
trunk directory to it. Then instantiate Steel using the following template:
steel_top core( .CLK( ), .RESET( ), .REAL_TIME( ), .I_ADDR( ), .INSTR( ), .D_ADDR( ), .DATA_OUT( ), .WR_REQ( ), .WR_MASK( ), .DATA_IN( ), .E_IRQ( ), .T_IRQ( ), .S_IRQ( ) );
Steel must be connected to a word-addressed memory with read/write latency of 1 clock cycle. It can be optionally connected to an interrupt controller and a real-time counter. Read the documentation to learn how integrate the core to these devices.
The author is a computer engineering student at UFRGS (graduates at the end of 2020) and developed Steel Core for his undergraduate thesis.
Contact: firstname.lastname@example.org / email@example.com
My colleague Francisco Knebel deserves special thanks for his collaboration with this work.