RISC-V Steel Core
RISC-V Steel is a free and open 32-bit processor core that implements the RV32I instruction set of the RISC-V architecture. It is designed to be easily reused in new RISC-V based hardware designs, from small embedded projects to complex systems on a chip.
Check out how to get the Hello World project running on an FPGA!
- RV32I base integer instruction set
- Zicsr Control and Status Register extension
- Machine-level privileged architecture
- AXI4-Lite Master Interface option
- 3-stage pipeline, in-order execution
- Passes all RISC-V Compatibility Test Framework tests
- Single source file (Verilog)
- Free and open-source (MIT License)
RISC-V Steel Core is distributed under the MIT License.
The project goal is to help expand the adoption of the RISC-V architecture by creating free and open RISC-V hardware that is easy to reuse.
Please open a new issue.
- RV32I base instruction set ✔️
- Zicsr extension ✔️
- Support to M-mode ✔️
- AXI4-Lite option ✔️
- Support to U-mode
- C extension
- M extension