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Details

Name: steelcore
Created: Jun 25, 2020
Updated: Jul 1, 2020
SVN Updated: Jul 1, 2020
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties

Category:Processor
Language:Verilog
Development status:Alpha
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: Others

About Steel Core

Steel is a 3-stage single-issue in-order RISC-V microprocessor core designed to be simple and easy to use. It is intended for use in FPGAs as the processing unit in embedded system designs.

Key features:

  • RV32IZicsr implementation
  • Small and easy to use
  • 3 pipeline stages
  • Single-issue
  • M-mode support
  • Targeted for use in FPGAs
  • Full documentation

Licence

Steel is distributed under the MIT License. See the LICENCE.md file.

Documentation

Steel documentation (https://rafaelcalcada.github.io/steel-core/) provides information on:

  • Steel configuration
  • Memory alignment rules
  • Integration with other devices
  • Implemented extensions and CSRs
  • Supported exceptions and interrupts
  • Trap handling
  • Implementation details
  • Timing diagrams for instruction fetch, data fetch, data writing and interrupt request processes
  • Input and output signals

Read the docs carefully before using the core.

Using Steel in your project

To use Steel in your project you must import all files from trunk directory to it. Then instantiate Steel using the following template:

steel_top core(

    .CLK(  ),
    .RESET(  ),        
    .REAL_TIME(  ),        
    .I_ADDR(  ),
    .INSTR(  ),        
    .D_ADDR(  ),
    .DATA_OUT(  ),
    .WR_REQ(  ),
    .WR_MASK(  ),
    .DATA_IN(  ),        
    .E_IRQ(  ),
    .T_IRQ(  ),
    .S_IRQ(  )

);

Steel must be connected to a word-addressed memory with read/write latency of 1 clock cycle. It can be optionally connected to an interrupt controller and a real-time counter. Read the documentation to learn how integrate the core to these devices.

About the author

The author is a computer engineering student at UFRGS (graduates at the end of 2020) and developed Steel Core for his undergraduate thesis.

Contact: rafaelcalcada@gmail.com / rafaelcalcada@hotmail.com

Acknowledgements

My colleague Francisco Knebel deserves special thanks for his collaboration with this work.