Gisselquist, Dan

Pipelined wishbone to AXI converter

reset input is REQUIRED, it should clear the axi master logic, fifos etc etc

reset signal missing

setting ID width to 1 causes synthesis error

ID width = 1 illegal

[IP_Flow 19-627] Port 'o_wb_addr': XPath expression failed: Undefined parameter "AW" used in expression "(AW - 1)".

this happens when trying to use IP wizard, not yet clear what the fix should be for this

vivado IP import error

[Synth 8-2576] procedural assignment to a non-register wb_cyc_stb is not permitted ["b:/SVN/cores/customers/Zifra/wb2axip-master/rtl/src/wbm2axisp.v":580]

procedural assignment to a non-register wb_cyc_stb is not permitted

[Synth 8-1751] cannot index into non-array reorder_fifo_valid ["b:/SVN/cores/customers/Zifra/wb2axip-master/rtl/src/wbm2axisp.v":565]

cannot index into non-array

[Synth 8-1031] reorder_count is not declared ["b:/SVN/cores/xyz/wb2axip-master/rtl/src/wbm2axisp.v":541]

reorder count not defined

`default_nettype	none

Problem with Xilinx Vivado!

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Pipelined wishbone to AXI converter