OpenCores

UART 16550 core :: Bugtracker

Request(s)
Date Title Status Assigned to Submitted by
Aug 4, 2006 about rs OPENED np02030418@tom.com
Aug 4, 2005 VHDL Implementation OPENED jaganj@myw.ltindia.com
Bug(s)
Date Title Status Assigned to Submitted by
Dec 8, 2010 Xilinx iSim generates "out of valid range" error OPENED c.noble
Aug 2, 2010 suggested receiver core fixes OPENED eteam
Mar 13, 2009 Fatal bug in uart_receiver.v: srx_pad_i is not synchronized at all OPENED ehliar
Nov 6, 2008 Problem with 16550 UART core OPENED valentina.lomi@intecs.it
Jul 19, 2007 TERI in Modem Status Register Not To Specification OPENED victor_chan@trimble.com
Nov 26, 2006 Does uart_int.v testcase run successfully? OPENED dmarris@charter.net
May 19, 2006 Need to fix commenting-out style in rtl/verilog/uart_defines.v OPENED jcollins@llnl.gov
May 15, 2006 Need to fix commenting-out style in rtl/verilog/uart_defines.v OPENED jcollins@llnl.gov
Oct 14, 2005 student OPENED paul_cooke_98@yahoo.co.uk
Jul 6, 2005 Typo in documentation OPENED spam@anschitech.de
Jan 25, 2005 Three bugs OPENED chenxj@wxintech.cn
Dec 21, 2004 wishbone SEL_I problem CLOSED luke.darnell@g2microsystems.com
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