The project files are checked in to SVN, available here:
This is a controller core for DDR3 SDRAM.
The testbench consists of a MicroBlaze MCS microcontroller with one module of glue logic to adapt it to the DRAM controller.
The glue logic module multiplexes the 256 bit data busses of the DRAM controller down to the 32 bit data busses of the MicroBlaze MCS.
The MB MCS only has 1GB of address space available in its IO port interface and the DRAM controller supports DIMMS of up to 8GB. The glue logic accounts for this by using a GPIO port from the MB MCS to provide the high order address bits, allowing SW running on the MB MCS to use a bank switching scheme to fully access DIMMS larger than 1GB.