Tota, Sergio

PIF2WB

## Description

This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.

## Features

\- PIF master support  
\- Wishbone slave support  
\- Burst transfers support  
\- VHDL RTL  
\- Fully synthesisable

## Status

\- RTL: Complete  
\- Document: Complete


<h2 id="description">Description</h2>
<p>This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.</p>
<h2 id="features">Features</h2>
<p> - PIF master support<br />
 - Wishbone slave support<br />
 - Burst transfers support <br />
 - VHDL RTL<br />
 - Fully synthesisable</p>
<h2 id="status">Status</h2>
<p> - RTL: Complete<br />
 - Document: Complete</p>


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PIF2WB

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