Annayya, Dinesh

8/16/32 bit SDRAM Controller

Hi,
When try to use 8/16/32 bit SDR Mode,I found Code and documentation is not match.
![](https://cdn.opencores.org/usercontent/75cff638890e4371ce40e6cc64123010fa9bee953a59eda6ab788dc197de393f.png)

![](https://cdn.opencores.org/usercontent/dc4feceb60d159f0f6d6e480a2e80eb7514eb2f961cf7d7af5ceb500caf6156e.png)

It seems that 8bit and 16bit are reversed.

The Code and documentation are not match

Can this controller support burst length(2,4,8, Full page)?
thanks

Full page busrt mode

I think there is a bug in IP core,if you want to use the SDRAM frequently, your write request and read request may be failed without any alarm from the IP core, for example you want to read a packet, the ip core give you read valid but the data bus is invalid. it is because in some situations IP core don't activate the SDRAM row and command a write or a read without activation so the SDRAM ignore the commands.if you request during the refreshing of the SDRAM I mean when "mgmt st" is one the IP core may forget to issue an activate command before read or write, you can check the rfsh_timer in your code before issuing read or write command to check if this is refresh time or not. in this way you can avoid such conflicts.

read or write failed

hello:
   I am using this core on  fpga. but, I can not access the maximum address of  sdram chip. for example, the  size of sdram chip is 8MB and is 2M32b, the maximum address of sdram is 0x1ffffc. when access this address ,can not get right result.
   yours.

can not access the maximum address of scram chip

there is a port named 'wb_cti_i' which is not in specification datasheet.
and my wish bone bus has not this port....
I want to know how to set this.

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8/16/32 bit SDRAM Controller