Wallner, Daniel

MikeJ

T80 cpu

Hi,

I use a t80 core with a Spartan 7 Xilinx FPGA and Vivado for RTL simulation.
When fetching a RET (return opcode 0xC9) instruction it should last 10 cycles according to CPU data sheet:

![](https://cdn.opencores.org/usercontent/5ee3897f41cd1344dc37fdaad8f3a7bbbaa0cb6ae28b16c1b604f3bed0408dc3.jpg)

However, when looking at RTL simulation, it last one more cycle (11 instead of 10 as expected):

![](https://cdn.opencores.org/usercontent/b7c1ad7de61ef5126fdf3422111d03571c82cad5014e838705d16299981c52c7.jpg)

Is it a know issue ? Could somebody have a look ?

Thanks,

Yann

RET instruction takes one more cycle

I was using the core the other day and saw some suspicious behavior with the OUTI opcode. Seems the HL register is not incrementing.  It just remains constant after the opcode executes.

I switched out the T80 core with the A-Z80 core out of curiosity and the code executed correctly.  

Thanks,
-Adam

OUTI doesn't increment HL

I build a system with t80s and the following generics:
      mode       => 1,  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
      t2write    => 1,  -- 0 => WR_n active in T3, /=0 => WR_n active in T2
      iowait     => 0,  -- 0 => Single cycle I/O, 1 => Std I/O cycle

In context of interrupt observed the following situation in IM2:
cycle 0: m1
cycle 1: m1&mreq&rd: read opcode x"db" (in a, (x10))
cycle 2: refresh, int_n becomes 0
cycle 3: refresh
cycle 4: 
cycle 5: mreq&rd: read x"10" from memory (port number)
cycle 6+7:
cycle 8: iorq&rd: read port x"10"
cycle 9:
cycle 10: m1
cycle 11: m1&iorq: read index of interrupt vector from IO device
cycle 12+13: refresh
cycle 14: mreq&refresh
...
cycle 22: put address of ISR-table-index to address bus
cycle 23: mreq&rd, same address as previous cycle (i. e. cycle 22)
It is expected that in cycle 23 the LSBs of the address equals the data value from cycle 11. However, the LSBs of the address are the value of the data bus in cycle 12. In this cycle the IO device does normally not provide the ISR table index.

Workaround: The data bus keeps always its value until a new value is put there.

Note: The reading of the ISR-table-index seem to work in other cases.

IM2: getting index of ISR table sometimes wrong

When executing the program in the FPGA simulation, an error was found in the memory filling - it is performed by the INIR command, writing 256 bytes blocks.
When debugging by means of SignalTap, it was found that the register pair of HL is not incremented. Register B successfully decrements to ALU.

INIR not incremented HL register

program:
EI
HALT

T80 enter halt state, INT later has no effect

T80 do not exit HALT in INT

Problem is simply about inserting WAIT_n in MEM_WR output of Z80.

Need is about having enought time to say to SDRAM : finally I'm not a ROM (@A) but a RAM (@B)... Amstrad CPC 6128 does that : if you write in ROM in fact you write in RAM hidden beside. All that with a poor SDRAM.

A hack is running actually, I add this component with "WAIT_n entry" (just for adding 1 MEM_WR pulse after having detected one MEM_WR rising edge) instead of using Z80 WAIT_n. This component is inserted before clock, and then does not respect Time Contraints at all :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity please_wait is
    Port ( CLK_n : in  STD_LOGIC;
           WAIT_n : in  STD_LOGIC;
           CLK_WAIT_n : out  STD_LOGIC);
end please_wait;
architecture Behavioral of please_wait is
begin
CLK_WAIT_n<=CLK_n or not(WAIT_n);
end Behavioral;

In Z80 datasheet, part "Memory Speed Control", you can :
* Figure 21. Adding One Wait State to an M1 Cycle, for slowing memory access about fetching instructions
* Figure 22. Adding One Wait State to Any Memory Cycle, for slowing memory access about MEM WR or RD

In T80.vhd you have :
 if TState = 2 and Wait_n = '0' then
 elsif

so if you insert a Wait_n during TState 2, you wait.
But this process is under a "CLK_n'event", against T80se.vhd "CLK_n'event"...
So the time T80se say me {RD_n,WR_n,IORQ_n,MREQ_n} hello, if I write response, TState is 2 in T80se but TState is 3 in T80.vhd... so I don't reach the thing.
Here the first "bug" (minor)... I think that 2 separate components is not a great idea here.

So then I added some constants in T80se in order to insert one/some WAIT_n (in T80.vhd T2) on "MEM_WR", but it does fail (my SDRAM controler is not validated but seems quite ok)
Here the second "bug" (major for Amstrad project)

Regards,

Renaud (FPGAmstrad)

Memory Speed Control

Hi,

The opcodes LD A,R and LD A,I don't change the flags H, N, Z and S correctly.

This make bugs in some games with ZX Spectrum cloned in FPGA.

The solution:

diff -Naur T80.vhd T80_fixed.vhd

--- T80.vhd     Sun Nov 24 13:51:28 2002
+++ T80_fixed.vhd       Tue May  6 19:10:00 2014
@@ -604,9 +604,25 @@
                                        when "00" =>
                                                ACC <= I;
                                                F(Flag_P) <= IntE_FF2;
+                                               if I = X"00" then
+                                                       F(Flag_Z) <= '1';
+                                               else
+                                                       F(Flag_Z) <= '0';
+                                               end if;
+                                               F(Flag_H) <= '0';
+                                               F(Flag_N) <= '0';
+                                               F(Flag_S) <= I(7);
                                        when "01" =>
                                                ACC <= std_logic_vector(R);
                                                F(Flag_P) <= IntE_FF2;
+                                               if R = 0 then
+                                                       F(Flag_Z) <= '1';
+                                               else
+                                                       F(Flag_Z) <= '0';
+                                               end if;
+                                               F(Flag_H) <= '0';
+                                               F(Flag_N) <= '0';
+                                               F(Flag_S) <= R(7);
                                        when "10" =>
                                                I <= ACC;
                                        when others =>


Thanks!!

Flags alteration with LD A,R and LD A,I

Whilst attempting to implement a GameBoy, I've discovered what I believe are bugs - or probably more correctly - unfinished implementations - of a few GameBoy instructions.

Most notably, LD ($FF00+C),A does not appear to be correct. The code looks (and behaves) like it was cut-and-paste from the LD (BC),A instruction microcode, and additionally asserts the IORQ signal. It would also appear that the complementary instruction LD A,($FF00+C) is similarly incomplete.

Is there any intention to complete implementation of the GameBoy mode in the near future? I'll attempt to fix/modify/add support for these instructions myself, but must admit so far I've found the implementation rather difficult to follow. No doubt that will improve with further study of the core...

GameBoy instructions

Using the T80a core in a "real-circuit-based" application, I got problems when I activated the part of the circuit using the WAIT_n signal.
Analysing the situation with a logic analyser, I found out that the behaviour of the RD_n and WR_n signals during wait cycles externally requested by WAIT_n='0' seems not to be correct. Both signals return to '1' during the wait cycles although an active RD_n or WR_n signal should remain active (='0') during wait cylces according to the Zilog datasheet - this may lead to corrupted memory accesses.
To make my application work I slightly modified T80a.vhd. If you are interested, I would be happy to provide the modifications --- just let me know! Best regards and thank you for the great work.

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T80 cpu