Burke, Tom

Fixed Point Math Library for Verilog

Hi ,

The qdiv module doesnt give the expected result. I am having a and b of width (Q,N) as (16,32). Quartus throws a warning saying, 

Warning (10230): Verilog HDL assignment warning at qdiv.v(95): truncated value with size 78 to match size of target (47)
Warning (10230): Verilog HDL assignment warning at qdiv.v(101): truncated value with size 78 to match size of target (32)

I am getting qout as zero.

qdiv not working

Hi, 
I was using the code of qmult.v
The sign bit is not assigned correctly if we multiply a negative number by 0.
Ideally the sign bit should be '0'. But the xor of the 2 sign bits (1 ^ 0) gives an incorrect value of 1.

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Fixed Point Math Library for Verilog