The VHDL Test Bench

Overview

The VHDL test bench is a collection of VHDL procedures and functions which allow the user to create their own scripting instructions for test stimulus. The stimulus script or test case contains the instructions in a regular ASCII text file. The function of the instructions is coded in VHDL as part of the test bench. The test bench VHDL package contains procedures to create instructions, read, parse and execute the test script (stimulus file, test case, script).

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June 10, 2009
This update of the Overview page was to clean up the duplicate text. An update fixing a current bug report, and request will happen shortly.

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June 20, 2009
Commit fix to variable addition/validation bug here: http://opencores.org?do=viewbug&bug=467
Update example to match the package version here: http://opencores.org?do=viewbug&bug=472

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April 19, 2014
Commit the VHDL Test Bench Package as is released on my privet download site.
This includes one minor fix, and one upgrade to enable an undefined number of parameters for a command.
Also, another example and a code snips file with more examples and code to copy.
Open Office does not enable the output of PDF files (my latest version ..), so only Open Office output is
included for the documentation. Details of the changes are document.

The ttb_gen_gui tool has also been updated to enable more VHDL syntax parsing. Multi pin definitions
on a single line are now supported.

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Aug. 19 2014
Change licensing of the VHDL Test Bench Package to BSD-2 clause
Remove duplicate copies of package files from packet_gen example
Remove old versions of ttb_gen application, rename most recent version to ttb_gen_gui

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June 5 2023

Some work has been done to improve the code of the test bench and bring it up to 2008. Also optimizations were done to improve the performance of the test bench code. This has been done in preparation for running on cloud based simulators like Metrics (dsim). Some significant improvements in runtime have been realized. The effort is on going and this update is to let users know that development of the VHDL test bench is still on going. The contents of the Git repo will be submitted to the OpenCores SVN repo once the package is known to be at a good level of quality. https://github.com/sckoarn/VHDL-Test-Bench The git repo is a working repo and this news is for those that may want to see the latest VHDL testbench.

Once the profile tests are complete, the package will again be changed so that line type is used instead of hard coded string lengths. This should bring yet more performance increases and general RAM use reduction.

This effort is being put in so that the VHDL testbench will be effective on cloud based simulation. Currently https://metrics.ca/ provides cloud based mixed language simulation.

Blog Link

I have started a Blog at this link:
http://vhdltb.blogspot.com