Borga, Andrea

Blankers, Roel

Schreuder, Frans

Verwoert, Leonie

Boukadida, Nayib

Kharraz, Oussama

Nikhef

Wupper: PCIe DMA Engine for Xilinx FPGAs

There are for some reason no buttons like "close issue" on bugs (eg https://opencores.org/projects/virtex7_pcie_dma/issues/7)

Can't seem to close issues on opencores.org

We miss the documentation of WupperCodeGen in the OpenCores.org version of Wupper.

Documentation about WupperCodeGen

I got an error that signal hk0/nReset has multiple drivers in Vivado 2017.4. After checking housekeeping.vhd, I found that the signal nReset is assigned twice on line 141 and line148 (an output port of i2c_interface.vhd).

nReset has multiple drivers

In my test project, I call data_from_host() routine. the data size is 1024 and the tlp is 256, so the wupper core will generate 4 req to host.The data from host seems to be out of order. the wupper core does not handle this condition!

data from host seems to be out of order

The Wupper documentation needs some updating

Documentation out of date

When you poll a register on a high frequency using multithreading, while DMA is busy, the PCIe bus locks, the only resolution is to reboot the PC.

PCIe lock when reading registers on a high frequency

In the PC => FPGA path, packets are missing due to 2 reasons:
 - the dma write process is not waiting when the tags are all occupied
 - the fifo in the user application should use prog_full in stead of full

Missing packets in receive (PC => FPGA) path

After triggering in Chipscope on an unrecoverable error, it appeared that when back pressure occurred just before the last word of the TLP, the tlast signal was asserted already on the second last word.

Wupper hangs after several GB of data at full speed

After long DMA transfer, several 100MB, the pcie endpoint locks up with Internal uncorrectable error.

Endpoint locks up after long transfers

When reading registers for the first time, they sometimes show a wrong value
same is true for the interrupt table.
writing is fine, just reading the value back is not always correct.
Possibly the synchronization between 40MHz and 250MHz needs attention

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Wupper: PCIe DMA Engine for Xilinx FPGAs