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Public Profile of Borga, Andrea
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Extended Profile
Info
Username
aborga
Fullname
Borga, Andrea
Email
aborga@openco... (@opencores.org)
Position
Digital Design Engineer
City
Amsterdam
Country
Netherlands
Extended Profile
aborga
LinkedIN
in/andrea-borga-44b386141/
Twitter
andyborga
Reddit
andyborga
Research Gate
Andrea_Borga
Projects
4
Core1990: Interlaken protocol
8
FPGA remote slow control via UART 16550
5
Wupper: PCIe DMA Engine for Xilinx FPGAs
26
WISHBONE Bus Specifications
6
Total
45 received
Starred projects
10
a VHDL 16550 UART core
CFI flash controller
Core1990: Interlaken protocol
gh vhdl library
I2C controller core
RadioHDL
SPI Master/Slave Interface
FPGA remote slow control via UART 16550
Wupper: PCIe DMA Engine for Xilinx FPGAs
WISHBONE Bus Specifications
Submitted bugs
3
Open
1
Open
WISHBONE Bus Specifications — gather more wishes for a B5 revision!
Closed
2
Closed
Wupper: PCIe DMA Engine for Xilinx FPGAs — Documentation about WupperCodeGen
Closed
FPGA remote slow control via UART 16550 — The importance of feedback!
Forum posts
23
23 posts in 3 forums
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