Doin, Jonny

SPI Master/Slave Interface

The spi_slave.vhd has a MUX at the MISO output that preloads the top bit of the shifter before any spi clock. 
BUG: the mux will glitch when CPHA='1' at the first clock edge.

MISO top-bit preload

In SPI_SLAVE.VHD, if the user does not write a new word (strobing 'wren_i') and the master sends more clocks (i.e., continuous transfer), the slave goes from state 1 to 0, then to state N .. 1 .. 0 again. This causes an error in bit sync, and received data has a 'bit shift' error.

SLAVE Continuous Tranfer

In spi_master.vhd

-- minimum prefetch lookahead check
    assert PREFETCH >= 2
    report "Generic parameter 'PREFETCH' (lookahead count) needs to be 1 minimum"

must be 2 minimum.

assert PREFETCH >= 2

The cores allow continuous transfer mode without any sck pauses. The slave core was not tested in silicon for the CT mode, but only in simulation.

Verify SLAVE continuous transfer mode

The CPHA='1' setup results in a SCK glitch at the end of the last word, causing an extra clock pulse on the bus.

CPHA='1'

The MOSI circuit of the spi_master core was verified in silicon for up to 50MHz SPI clock, in a 100MHz Spartan-6. Timing analysis show that it may go up to 150MHz. This is very useful for output-only high speed ports.
Now the MISO has to be verified for its top speed.

After that, a ARM uC will be the reference testing interface, running SSP at 36MHz.

Verify MISO top speed

<reminder to self> Change SPI clock generation, that now is a clock divider, to a clock-enable structure, keeping a single high-speed clock for the core. This will streamline GCLK buffers for the whole design, and may improve max frequency.

Single clock

internal samp_clk appears to stay in phase relative to sck_o regardless of CPHA setting. (CPOL = 0 for the case I tested).  Expected behavior (if I'm reading the code comments correctly) is for samp_clk to switch phase relative to sck_o depending on CPHA setting.

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SPI Master/Slave Interface