Written in:Any languageVHDLVerilog & VHDLVerilogSystemCBluespecC/C++Other

Stage:Any stagePlanningMatureAlphaBetaStable

License:Any licenseGPLLGPLBSDCERN-OHL-SCERN-OHL-LCERN-OHL2-POthers

Wishbone version:Any versionB.3B.4

ASIC proven

Design done

FPGA proven

Specification done

OpenCores Certified

Arithmetic core 119

Prototype board 42

Communication controller 218

Coprocessor 10

Crypto core 81

DSP core 49

ECC core 24

Library 21

Memory core 51

Other 119

Processor 227

System on Chip 86

System on Module 2

System controller 21

Testing / Verification 37

Project	Files	Statistics	Status	License	Wishbone version
Boost Converter		Stats		LGPL
Bus Transaction Monitor with JTAG		Stats		LGPL
c - VHDL Co-Simulation with FLI		Stats		Others
Constrained random test generator		Stats		LGPL
Diagnostics library		Stats		Others
DS1621 model		Stats		LGPL
EziDebug		Stats		LGPL
fast behavioral transceiver simulation models		Stats		Others
FPO (Logic Analyzer)		Stats		GPL
FROM and TO files		Stats		LGPL
Generic AHB master stub		Stats		LGPL
Generic AHB slave stub		Stats		LGPL
Generic APB master stub		Stats		LGPL
Generic APB slave stub		Stats		LGPL
Generic AXI master stub		Stats		LGPL
Generic AXI slave stub		Stats		LGPL
HASM TestBench Vector Generator		Stats		LGPL
High Load configurable test project		Stats		BSD
i2clcd		Stats		LGPL
JTAG Test Access Port (TAP) Verilog		Stats		LGPL
LogicProbe		Stats		BSD
Open Cores AXI Bus Functional Model for Intel Platform Designer/Altera-ModelSim		Stats		LGPL
Open JTAG project		Stats		LGPL
PlTbUtils		Stats		LGPL
PRBS Signal Generator and Checker		Stats		LGPL
Simulation tools library		Stats		Others
SocExplorer		Stats		GPL
socgen		Stats		LGPL
Soundfile Testbench		Stats		BSD
StaplPlayer		Stats		LGPL
SystemVerilog Directed Test Bench		Stats		Others
The VHDL Test Bench		Stats		BSD
UART observer		Stats		LGPL
Uart2BusTestBench		Stats		LGPL
VHDL Whisbone Test Bench		Stats		LGPL	B.3
Video Pattern Generator		Stats		LGPL
Wishbone Scope		Stats		GPL	B.4

Video controller 50

Uncategorized 94