Written in:Any languageVHDLVerilog & VHDLVerilogSystemCBluespecC/C++Other

Stage:Any stagePlanningMatureAlphaBetaStable

License:Any licenseGPLLGPLBSDCERN-OHL-SCERN-OHL-LCERN-OHL2-POthers

Wishbone version:Any versionB.3B.4

ASIC proven

Design done

FPGA proven

Specification done

OpenCores Certified

Arithmetic core 53

Prototype board 8

Communication controller 89

Coprocessor 4

Crypto core 44

DSP core 24

Project	Files	Statistics	Status	License	Wishbone version
Adaptive LMS equalizer		Stats		GPL
all-pole IIR filters		Stats		LGPL
Canny Edge Detector		Stats		LGPL
Correlation statistics core		Stats		Others
DDS Synthesizer		Stats		LGPL
DSP WishBone Compatible Cores		Stats		LGPL
FFT-based FIR Filter		Stats		LGPL
filtro_FIR		Stats		LGPL
Floating-point FFT/IFFT		Stats		LGPL
Fully Pipelined Roberts, Prewitt, Sobel, Scharr Edge Detectors		Stats		LGPL
G-FIR TF/DF		Stats		GPL
Generic FIR Filter		Stats		LGPL
Hilbert Transformer		Stats		LGPL
IQ Phase and Gain Correction		Stats		LGPL
Low-Pass IIR Filter		Stats		LGPL
NCO / Periodic Waveform Generator		Stats		GPL
Pipelined DCT/IDCT		Stats		LGPL
Polyphase Filter		Stats		Others
Quadrature Oscillator		Stats		LGPL
Radix-2 SDF FFT		Stats		Others
triangle wave		Stats		LGPL
VIIRF - Versatile IIR Filter		Stats		Others
Wideband FFT		Stats		Others
Wideband Polyphase Filter Bank		Stats		Others

ECC core 9

Library 12

Memory core 16

Other 50

Processor 93

System on Chip 33

System controller 9

Testing / Verification 13

Video controller 20

Uncategorized 7