Hutchison, Guy

M. Harte, Howard

TV80

Instruction DJNZ fails like this:

ADDR  Instruction
------------------
00E6  ld bc,$0000
00E9  djnz $00E9
00EB  di
00EC  dec c
00ED  jr nz,$00E9

TV80 does not loop around 00E9 but just continues on to 00EB.

I simulated this with iVerilog. I can provide waveforms if you contact me.

Thanks.

DJNZ/DEC fails

In "tv80_core.v", at lines 1333-1334, there are missing elements in the sensitivity list.
Below, the patch that correct that problem:

				      +++

--- tv80_core_ss_2015-11-12_1757.v	2015-11-12 17:57:31.712532800 -0500
+++ tv80_core.v	2015-11-12 18:04:43.443226400 -0500
@@ -1330,8 +1330,9 @@
         end
     end
 
-  always @(/*AUTOSENSE*/BTR_r or DI_Reg or IncDec_16 or JumpE or PC
-	   or RegBusA or RegBusC or SP or tstate)
+  always @(	/*AUTOSENSE*/
+		 		BTR_r or DI_Reg or IncDec_16 or JumpE or PC or RegBusA or
+				RegBusC or SP or tstate or ID16_B or PC16_B or SP16_A or SP16_B)
     begin
       if (JumpE == 1'b1 ) 
         begin
@@ -1370,7 +1371,8 @@
       ID16 = RegBusA + ID16_B;
       PC16 = PC + PC16_B;
       SP16 = SP16_A + SP16_B;
-    end // always @ *
+
+    end	//	always @ ...
   
 
   always @(/*AUTOSENSE*/IntCycle or NMICycle or mcycle)

				      +++


Regards,
From a tv80 user.

Claude

"tv80_core.v" have missing elements in a sensitivity list

Hi, 

First forgive me for disturbing you, i am new to FPGA so i may be using the wrong files from the download, files i used are from tv80_latest(1).tar.gz\tv80\trunk\rtl\core\*.* i presummed these are the most recent files. So i used the Z80 core to develope a ZX81 clone on FPGA, the ZX81 usws some tricks to generate the display and relies on exact cycle timing... I found after looking elsewhere that the RET instruction appears to be taking 11 clock cycles instead of 10 as it should. I corrected this behaviour by making a single change to tv80_mcode.v

on line 1483 from    TStates = 3'b101;
changed to           TStates = 3'b100;

I hoe this is useful for you.

Regards Andy Rea

RET timing/

tv80_core.v, line 1325: missing in sensitivity list: ID16_B, PC16_B, SP16_A, SP16_B

i'm assuming they are missing since this always block looks like it is combinational.

incomplete sensitivity list

the output port of tvcore changed from being named do, to being named dout. (why was it changed?)

tv80n is still using do

tv80n, do not changed into dout

The zero flag and negative flag are not set properly when a LD A,R or LD A,I instruction is executed. The test case for this had been removed. Upon properly setting the flags, the test cases work correctly.

See pages 98 and 99 of Zilog Z80 User Manual UM008001-1000


tv80_core.v @734
                 if (Special_LD[2] == 1'b1 ) 
                    begin
                      case (Special_LD[1:0])
                        2'b00 :
                          begin
                            ACC <= #1 I;
                            F[Flag_P] <= #1 IntE_FF2;
                            // Joe
                            F[Flag_Z] <= (I == 0);
                            F[Flag_S] <= I[7];
                            F[Flag_H] <= 0;
                            F[Flag_N] <= 0;
                            // END JOE
                          end
                        
                        2'b01 :
                          begin
                            `ifdef TV80_REFRESH
                            ACC <= #1 R;
                            `else
                            ACC <= #1 0;
                            `endif
                            F[Flag_P] <= #1 IntE_FF2;
                            // Joe
                            F[Flag_Z] <= (I == 0);
                            F[Flag_S] <= I[7];
                            F[Flag_H] <= 0;
                            F[Flag_N] <= 0;
                            // END JOE
                          end

Flags for LD A,R and LD A,I

Undocumented instructions like RL (IX+1),E are not supported by TV80.

In real Z80 all instructions under CB can be prefixed by DD/FD. In result will be operation like: OP (II+d),r, where II is IX or IY, d - offset (-128...+127), r one of standard registers (A, B, C, D, E, H, L). This operations do something like:
ld r,(II+d)
OP r
ld (II+d),r

OP can be: RLC, RL, RRC, RR, SLA, SRA, SRL, SLL, BIT, SET, RES

OpCode: DD CB dd oo, there CB oo is code of "OP r" operation.

TV80 does not support some undocumented instructions

in tv80_core.v line 1242,
 original: Pre_XY_F_M<=#1 mcycle;
 should be Pre_XY_F_M <=#1 (mcycle[0])? 1:
                           (mcycle[1])? 2:  
                           (mcycle[2])? 3: 
                           (mcycle[3])? 4:
                           (mcycle[4])? 5:
                           (mcycle[5])? 6:7;

a minor bug in tv80_core.v

Am utilising a couple of TV80 cores. Using ancient code written back in the 80s where INT is not cleared by M1 / iorq but persists until cleared by a write late in the ISR. If an NMI occurs during this time (i.e. INT lo) the vector for the NMI (0x66) is pushed to the stack as if it were the next instruction address and the code is vectored to 0x0038 i.e. it reenters the ISR it is already in. 
Interesting!

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