Witt, Sebastian

UART16750

Hello,

I'm simulating the design using Modelsim Actel 6.6d, but I'm having an undefined value for the SOUT signal.

However, when I verified the internal signal iSOUT, it seems to be correctly.
I also verified the signal imcr_loop and it seems to be ok.

Even at the begin of the simulation, when the reset is asserted, the value of iSOUT is undefined.

I think there is a problem with the process UART_OUTREGS in the uart_16750.vhd file.


Thank you,

Regards,

Diego BOTERO
diego.botero@hotmail.com

SOUT is Undefined

Hello,
I am trying to use this core in a Spartan 6 connected to a Arm processor.  In order to get the timing of the link between the ARM processor and the Uart16750 core I wanted to know what manufacture did you base your timing interface of the Uart16750 off of?

Currently I am trying to use the TI TL16c750 datasheet as a reference for the timing interface to the Uart16750 core.  I wrote a simple test that writes to the SCR scratch register, then clears the data bus, then reads the SCR scratch register and verifies it is the data we wrote to it.  This works for a couple of writes and reads but then fails randomly.  When it fails it reads back the data that was previously written to the SCR register and not the data that was just written to it.  This is what is leading me to believe I have a timing issue and wanted to see if you can point me to the correct datasheet I should be using for the timing values of the Uart16750 interface.

Uart Timing Datasheet Manufacture

In "uart_16750.vhd"
in the process UART_LSR,
the reset value for iLSR_FIFOERR is missing.

Missing Reset Value for iLSR_FIFOERR

It looks like the baud rate generator counts from 0 to DIVIDER.  To match a real 16750, I think it should count from 0 to DIVIDER-1.  The example is with a 1.8432 MHz clock and a baud rate of 115200, DIVIDER should be 1, and the 16x clock should be 1.8432 MHz.

Baud Rate off by 1?

From what I can see in the design there is possibly no transmisson/receive tests carried out on the design as there is not a test Uart connected to the DUT uart. Is this the case or has further work been carried out here?

Clearly I can see that a complete register test is carried out, but the asynchronous testing seems to be missing from the test bench. So I would imagine this may of been carried out in hardware only? Can you advise here please.

Testbench Questions

Should DDIS be high on reset not low...?

    UART_OUTREGS: process (CLK, RST)
    begin
        if (RST = '1') then
--            DDIS     <= '0';	--original
	    DDIS     <= '1'; --- corrected
            BAUDOUTN <= '0';
            OUT1N    <= '0';
            OUT2N    <= '0';
            RTSN     <= '0';
            DTRN     <= '0';
            SOUT     <= '0';
        --elsif (CLK'event and CLK = '1') then
        elsif rising_edge(CLK) then

Also CLK'Event ... is very old

DDIS

hello,


i want to simulate the design in modelsim tool, how to do, i am a beginner.
file given in bench i used but no wave form observed. how to see in modelsim tool.
if any notes sort of thing plz upload it, will be very helpful for me to learn.

simulate design in modelsim

hello.

the handling of cs/wr/rd seems strange to me.
i didn't know if they were high- or lowactive, so i had a look into the sourcecode.

then i stumbled over this:
   iCSWR  <= '1' when CS = '1' and WR = '1' else '0';
    iCSRD  <= '1' when CS = '1' and RD = '1' else '0';
    UART_ED_WRITE: slib_edge_detect port map (CLK => CLK, RST => RST, D => iCSWR, FE => iWriteFE);
    UART_ED_READ:  slib_edge_detect port map (CLK => CLK, RST => RST, D => iCSRD, FE => iReadFE);
    iWrite <= '1' when iWriteFE = '1' else '0';
    iRead  <= '1' when iReadFE  = '1' else '0';

the way i read this, you are detecting a falling edge on (CS and WR). meaning that when EITHER ONE of them goes low, you have a falling edge. i assume that this is not what you had in mind?

cs/wr/rd

Hi Sebastian.

Many thanks for your answer.

I have found my problem using your Quartus project given (for testbench i suppose). I see that you instanciate slib_clock_div with a 18 parameter (a divide by 18 main clock signal to drive BAUDCE)
Two things I doesn't understand :

1- What is BAUDCE input ?
2- Why RCLK is connected to BAUDOUTN?

My design have a main clock at 20.48 MHZ and I would like to communicate at 115200 Bauds. At wich rate should I drive BAUDCE ? Could you help me ? Have you got a 'datasheet' or something like ?

Best regards.
Chris.

Bug in Receiver interrupt

Hello,

I have tested you block in a CycloneII (EP2C8T144I8) and I didn't have any interrupt working on receiver. Then I check values of IER and FCR but it seems to be right. Progressing to resolve my problem I see some message on Analysis & synthesis. Here are the messages :

Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(226): object "iFCR" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(234): object "iIER_ERBI" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(235): object "iIER_ETBEI" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(236): object "iIER_ELSI" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(237): object "iIER_EDSSI" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(240): object "iIIR_PI" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(241): object "iIIR_ID0" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(242): object "iIIR_ID1" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(243): object "iIIR_ID2" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(244): object "iIIR_FIFO64" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(306): object "iRInRE" assigned a value but never read

I undrestand why I didn't receive any receiver interrupt...
Have you got any idea to correct this ??
Thanks for your answer.
Chris.

Browse

UART16750