Litochevski, Moti

MULLER, Steve

UART to Bus

Can you explain the calculation formulas of the two parameters baud_freq and baud_limit in detail?
After reading the formula, I have been unable to understand how the formula was generated.

Parameter Calculation Formula Questions

At binary mode protocol:
When you are sending constant zero byte, then sending NOP command with ack flag (bit 0) = zero at UART rx module, I see the ack is still recieved at UART tx module.

Ack is received for binary NOP command even if ack bit was zero

In file baud_gen.v line 9, written
"baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq";
I think it should be "baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate))",is it right? if not,can you explain the formula? thank you!

wrong comment about baud_limit in line9 in baud_gen.v file

According to document, in Text mode, the data and address shall send in HEX format, shall not be in ASCII code for each nibble.
Either the document shall fix or RTL shall fix.

The text mode data and address phase shall not be send by ASCII code

The opencores page specifies a BSD license but no license file is included in the source code, could this be corrected?

License Not in Source Code

The opencores page specifies a BSD license but no license is included in the source code.  Could this be corrected?

License Not in Repository

Force wrong prefix on the DUT serial input port let it be in unexpected state and can't respond to any valid command after that

Dead State

Thanks for sharing this core. 
uart_tasks.v cannot compile by ModelSim.

It produces 3 errors:

Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
** Error: (vlog-2155) Global declarations are illegal in Verilog 2001 syntax.

** Error: (vlog-2730) Undefined variable: 'serial_out'.

** Error:  Verilog Compiler exiting

Can you help or is there any one with same issue? Thanks

uart_tasks.v

uart_rx have some receive err bit when i set baud rate 115200bps,and clk run 100Mhz.i test it in binary mode

uart_rx have some receive err bit

A minor comma error in file:calc_baud_gen.sce line:25, and there is no x_message_modeless function in Scilab 5.3 for windows,so please change it to messagebox.

Script error need to be corrected

Is there an SDC timing file for this project? I am trying to build this project for an Altera device, and the compiler is requesting an SDC file.

Critical Warning: Synopsys Design Constraints File file not found: 'uart2bus_top.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.

SDC file

The code submitted here is in VHDL... But in the language feild its Verilog...

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UART to Bus