Rhoads, Steve

Plasma - most MIPS I(TM) opcodes

Hello, 

I am working on Plasma processor to make a multi-processor system out of it connected with a NoC. I would also like to know whether it is capable of handling video applications and does it have VGA support or not. 

Also, are any cache coherency protocols or semaphores implemented or not (in case of parallelism). 

Your assistance is kindly appreciated in advance.

Question regarding VGA support and parallelism

Hi, 

This is the output of test program running on mlite emulator:

***********************************************************************
2088880171: two billion '??? eight million eight hundred '??? thousand one hundred '??? one
1971673217: one billion nine hundred '??? one million six hundred '??? three thousand two hundred seventeen
1620052355: one billion six hundred twenty million '??? two thousand three hundred '??? five
0565189769: five hundred '??? five million one hundred '??? nine thousand seven hundred '??? nine
************************************************

When I run the same program using modelsim, the program goes into a kind of infinte loop. here is the output:
*******************************
0000000003: three
0000000003: three
0000000003: three
0000000003: three
0000000003: three
0000000003: three
0000000003: three
0000000003: three
0000000003: three
0000000003: three
***************************

I have tested different cross compilers (mips-elf, mips-gnu-linux ...) but nothing worked. 
Did someone have had the same issue ?  
Thanks for helping

compile and run

Hi.

When using vsim, I encountered the following error:

# Loading design_library.ram16x1d(ram16x1d_v)
# ** Fatal: (vsim-3420) Array lengths do not match. Left is 16 (15 downto 0). Right is 8 (0 to 7).
#	Time: 0 ps  Iteration: 0  Instance: /tb/proc0/u4_reg_bank/xilinx_16x1d/reg_loop(0)/reg_bit1a File: unisims/primitive/RAM16X1D.vhd Line: 32
# FATAL ERROR while loading design
# Error loading design
Error loading design
Command exited with non-zero status 12

The issue was solved changing the init value in RAM16X1D declaration in mlite_pack for 0x0016 instead of 0x16!

Hope it helps!

Simulation Modelsim PE 12.1

I found two problems in signed multiplication and division.

Problem 1 -- multiplying a negative number by zero gives an incorrect answer.
Example: -1 * 0
I expect: 0
Plasma gives: -0x100000000
I think sign_reg should be '0' when either of the operands is zero.

Problem 2 -- a division with a negative dividend gives a positive remainder.
Example: -6 % 12
I expect: -6
Plasma gives: 6
I think resulting upper_reg should be negated in this case.

Thank you for your consideration.

Signed multiplication/division

Hi, Rhoads
In ddr_control.vhd, there is a state called STATE_POWER_ON. Does all the initialization in ddr_init.c run on this state? 
Once the  initialization complete, state jumps to STATE_IDLE, right? Why we need to run  MemoryRead(DDR_BASE) 100 times after the initialization ? 

Thank you in advance.

ddr_control

1.In your control.vhd  line 448, rs = "111111";  --interrupt vector,
what's the function of interrupt vector? I checked interrupt vector(0x3c)'s data flow and found it ended in alu. It doesn't transfer to other modules any more.  Then, how interrupt vector works? 
2. In your reg_bank.vhd, you considered the situation when rs_index or rd_index are 101100. rs_index  and rd_index come from control.vhd, but control.vhd doesn't output 101100 at all. Why you consider the situations when rs_index or rd_index are 101100?

interrupt

Hi,Rhoads,it's me again
I am reading your code eth_dma.vhd.
1. Line 110 :  "send_level <= data_w(8 downto 0);"
What's the meaning of send_level? Does it mean the words waiting to transmit? 
If yes, do we need to tell eth_dma the numbers of words waiting to send using C or assembly language?  
2. I noticed that even we send data,which only need to read data from DDR, we still do this "data_write <= data_w;" (line 172), why? 
3. Why you use address 0x13ff0000 and 0x13fe0000, any special consideration?

eth_dma

In the overview page, you describe an add instruction. Stage#0 1 2 3 4. I think this is the datapath of an add instruction, right? 

Are the word "stage" in "two stage pipeline" and "Stage#0 1 2 3 4" the same meaning?

pipeline

Dear rhoads:
Plasma is an excellent project. I am enjoying hacking it. 
I have understood all the modules of mlite_cpu except mem_control.vhd. 
Assume the pipeline is two stage. 
Can it output opcode every clk cycle? Will memory read/write take two cycles?
when input pause_in can get its value and what's its function in FSM? 
Can you give me a description about how a LW instruction works? 
um, in fact I have got tangled in them for many days, help!  Thank you!

MEM_CONTROL

hello Mr rhoads

I use your processor to describe an ASIP witch do morphological operations. But when examining your vhdl code I can not understand first why do you divise the clock by 2 knowing that the FPGA eval board contains a clock tree that gives you the desired frequency.Second, about the Mult bloc why it takes 32 cycles to achieve the division ? thank you

Plasma Core running

Hello, 
I am a FPGA newfish. I have did all the steps as a Lab guide written by a professor and got the greetings from the boot loader.
But When I am trying to send bin files(opcodes, pi, count) to Plasma, I lose response. The program doesn't run at all. 
Can you spend a little time to help me ?
I am using Xilinx Spartan 3E starter board.

Has no response after bootloader's greeting

Hello
When I am trying to understand the code of plasma 32 bit core, I have found that the irq_status <= gpioA_in(31) & not gpioA_in(31) wich means that irq_status will have all the time '0'. Is it true?

irq_status <= gpioA_in(31) & not gpioA_in(31) &
                 irq_eth_send & irq_eth_rec & 
                 counter_reg(18) & not counter_reg(18) &
                 not uart_write_busy & uart_data_avail;
Thanks.

Plasma 32 bit Core

spartan-3e+ubuntu 12.04

Hello.
Can you help me, by suggesting a documentation of a similar file system  to the one provided at filesys.c?
Thank you in advance.

File System

Hi,
I tried to implement Plasma_Cpu on the Spartan-3A FPGA Starter Kit XC3S700A.
I just change the spartan3e.ucf, but while the mapping, there is this error; 
MapLib:30 - LOC constraint N11 on SF_A<23> is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

I replaced the UCF constraints for the StrataFlash address pins, which correspond to the Intel StrataFlash Parallel NOR Flash (SF) Spartan 3E, with the UCF constraints for the Flash address pins Parallel NOR Flash PROM (NF)which correspond to the Spartan-3A FPGA Starter Kit XC3S700A.

Thank you
drgbie

Plasma on Spartan3A  XC3S700A

Untitled bug

Hello,
When I try to "make count", I get this result whereas there is only one cygwin1.dll on my disk.

abeaugui@NTTSIME10 /c/Users/abeaugui/Desktop/plasma/trunk/tools
$ make count
C:\Users\abeaugui\Desktop\plasma\trunk\gccmips_elf\as -o boot.o boot.asm
c:\Users\abeaugui\Desktop\plasma\trunk\gccmips_elf\as.exe: *** conflicting versi
ons of cygwin1.dll detected.  Use only the most recent version.

    0       0 [unknown (0x1ED4)] (unknown) 0 lock_pinfo_for_update: rc 0, pinfo_
mutex 0xFFFFFFFF, Win32 error 6
make: *** [count] Error 1


Why?
Thak you
Alexandre

cygwin1.dll conflict

Hello Steve,

I noticed that the binary generated from compiling count.c does not match the included code.txt. I've simulated your core in modelsim and receive a correct output.txt file when the original provided code.txt is used. However, when I replace code.txt with the binary that is generated from compiling count.c, I simply receive an output file that says "Done". 

I noticed that under the Tools tab and in the Modelsim Simulation section, the code.txt you reference is the one that results from compiling count.c and I am confused by this. 

I was under the impression that the binary generated from compiling count.c should be the same as the provided code.txt. Am I incorrect in this thinking? Is perhaps one binary (the provided one) only for simulation, whereas the compiled one is for emulation? Thank you in advance for your help!

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Plasma - most MIPS I(TM) opcodes