Girard, Olivier

openMSP430

As reported by Thuan on the discussion group, there is an issue preventing the software development tools to connect to a COM port on Windows 10:
https://groups.google.com/forum/?fromgroups#!topic/discuss_openmsp430/3qDC6R-7Wig

Debug tool issue preventing COM port connection on Windows 10

The documentation refers to per_wen, which should be per_we.

per_wen -> per_we

The documentation refers to BCSTL1 and BCSTL2. That seems to be a misspelling of  BCSCTL1 and BCSCTL2 (right?). Furthermore, the addresses for DCOCTL and those registers is documented as the (non-standard) addresses 0x0004, 0x0006, 0x0008, but it seems that the implementation actually uses the standard addresses (0x0056, 0x0057, 0x0058).

BCSTL1, BCSTL2, DCOCTL spelling & addresses

Dear Oliver,

I have implemented the openMSP430 on my Opal Jelly board with Spartan3 FPGA. It works fine until I traced program by the minidebugger. Download instructions through UART port to PMEM works successfully. However, when I step through the assembly, some instructions e.g. jmp makes the pc fly to strange addresses such as 0x7..., but should be 0xf042 for instance.

The icarus verilog simulation works perfectly, I think it can be wrong instructions are transferred to the FPGA. Have you or anyone else meet this behavior? 

Best regards,
Zheng

regarding mini-debugger

The Get-Register procedure in the proxy was not updated to the new 32-bit matter. I made the following changes in the commands.tcl and the debugging problems are gone:

#-----------------------------------------------------------------------------#
# Read CPU registers                                                          #
#-----------------------------------------------------------------------------#
proc rsp_g {CpuNr} {
    
	global mspgcc_compat_mode

    # Read register value
    set reg_val [ReadRegAll $CpuNr]

    # Format answer
    set rsp_answer ""
    for {set i 0} {$i < [llength $reg_val]} {incr i} {

        regexp {0x(..)(..)} [lindex $reg_val $i] match msb lsb
		if {$mspgcc_compat_mode} {
        	append rsp_answer "$lsb$msb"
		} else {
			append rsp_answer "$lsb${msb}0000"
		}
    }

    return $rsp_answer
}

#-----------------------------------------------------------------------------#
# Write CPU registers                                                         #
#-----------------------------------------------------------------------------#
proc rsp_G {CpuNr cmd} {
    
	global mspgcc_compat_mode
	
    # Format register value
    if {$mspgcc_compat_mode} {
		set num_reg [expr [string length $cmd]/4]
	} else {
		set num_reg [expr [string length $cmd]/8]
	}
    set reg_val ""
    for {set i 0} {$i < $num_reg} {incr i} {
		
		if {$mspgcc_compat_mode} {
			set lsb "[string index $cmd [expr $i*4+0]][string index $cmd [expr $i*4+1]]"
			set msb "[string index $cmd [expr $i*4+2]][string index $cmd [expr $i*4+3]]"
		} else {
			set lsb "[string index $cmd [expr $i*8+0]][string index $cmd [expr $i*8+1]]"
			set msb "[string index $cmd [expr $i*8+2]][string index $cmd [expr $i*8+3]]"
		}
        lappend reg_val "0x$msb$lsb"
    }

    # Write registers
    WriteRegAll $CpuNr $reg_val

    return "OK"
}

Proxy has problems with RedHat/TI GDB Debugger

Hello Olivier Sir,

I have successfully implemented the LED blinking application with the openMSP430 processor on Xilinx Kintex7.

Now I want to implement hardware UART application on the processor. I followed the procedure as per the documentation and project example. The procedure is as follows:

1. Debugged through UART by selecting switches SW0/SW1 = 0/0.
2. then using switch configuration SW0/SW1= 0/1, I tried to access it on terminal window.  I have tried to get the output on  the terminal window tool like Minicom for Linux and Hercules, hyperterminal for Windows.

I have successfully loaded the HW_UART .elf file but I am unable to get the output on the terminal. 

can you please help me with the same..

Hardware UART communication issue

Hello, 

it is possible to deactivate the Memory access (CEN=1) in the reset state of the OMSP430. Backgorund, in an ASIC project we have to prepare the OMSP Memory implementation, and it is easier to this, when the MSP430 doesn't lock the memory via the CEN signal. 
Exists special reasons to do that in the other way (RST_N='0' -> CEN='0')? 

Best Regards, 
Andreas

Disabling PMEM in Reset

When you close the window(like minidebug) with the X, then it won't be close correctly.
You can simply add the next lines:
wm protocol . WM_DELETE_WINDOW {
    if {[tk_messageBox -message "Quit?" -type yesno] eq "yes"} {
       clearBreakpoints
       utils::uart_close
       exit
    }
}

Windows closing

Hi guys,

I've found some problems in the combobox library. If you use the tool programs in a multi-window environment, the combobox will open in the screen on the left. Therefore you have to remove the vrootx variable from the line 1062 
 ---new-->>> set x  [expr {$rootx}]

Combobox

Hello Everyone,

in the OMSP430 are the bits 7-5 and 3-1 reserved in register IE1 (0x0000) and IFG1 (0x0002). I write at the moment on an SPI module which implements the TIs SPI Module (only SPI mode). When I now connect this SPI IRQ to the corresponding channels, I can't use the Mask & Flag Register cause these bits are stucked by the HDL.

The belonging line in the verilog is
omsp_sfr.v (line 189)
assign  ie1 = {3'b000, nmie, 3'b000, wdtie};

It is possible to disable/enable the IRQ Channel 4/5 (SPIRX/SPITX) with these two bits?

Thanks for your reponse!

Best Regards.

SPIRX/SPITX IE1/IFG1

Hi,

I noticed that e.g. ta_cci0b on the timer module is mixed to the per_dout port without synchronization. There is a synchroniser on this signal (sync_cell_cci0), so maybe cci0_s can be used in tacctl0_full instead of cci0?
I guess similar logic is present on other signals.

Alternatively, all async inputs could be synchronized first before use in the module. This would cost some additional synchro flops.

Cheers,
Johan [for ICsense N.V.]

unsynchronized peripheral bus bits in TimerA

Hello,

it is possible to deactivate the Memory access (CEN=1) in the reset state of the OMSP430. Backgorund, in an ASIC project we have to prepare the OMSP Memory implementation, and it is easier to this, when the MSP430 doesn't lock the memory via the CEN signal.
Exists special reasons to do that in the other way (RST_N='0' -> CEN='0')?

Best Regards,
Andreas

Hello Oliver,

I'm trying to port openMSP430 to Artix-7.Now,I am troubled by one question.
I compile the C program with IAR and get HEX files,next I transform hex files to coe and initialize the RAM gengrated by ISE.When I run some simple programs without using TIMERA and I'll get the right result,however,I was wrong when I run the programs which enter LPMx modes.I do not where is wrong.
For example,the C program as follow:

#include <msp430x44x.h>
void main(void)
{
WDTCTL=WDTPW+WDTHOLD;
FLL_CTL0|=XCAP14PF;
TACTL=TASSEL0+TACLR;
CCR0=512-1;
CCTL1=OUTMOD_7;
CCR1=384;
CCTL2=OUTMOD_7;
CCR2=128;
P1DIR|=0x04;
P1SEL|=0x04;
P2DIR|=0x01;
P2SEL|=0x01;
TACTL|=MC0;
for(;;)
{
_BIS_SR(LPM3_bits);
_NOP();
}
}

The HEX file as follows:
:020000020000FC
:1080000031400006B0120C80B0125A80B240805A43
:108010002001F2D020005300B24004016001B240C0
:10802000FF017201B240E0006401B24080017401BE
:10803000B240E0006601B24080007601E2D2220048
:10804000E2D22600D2D32A00D2D32E00B2D0100022
:10805000600132D0D0000343FC3F30405E803040AE
:048060006280FF3FFC
:02FFFE00008081
:040000030000800079
:00000001FF


and the coe file as follows(I'm using 16bits RAM as PMEM):
memory_initialization_radix=16; 
memory_initialization_vector = 
4031 0600 12B0 800C 12B0 805A 40B2 5A80 
0120 D0F2 0020 0053 40B2 0104 0160 40B2 
01FF 0172 40B2 00E0 0164 40B2 0180 0174 
40B2 00E0 0166 40B2 0080 0176 D2E2 0022 
D2E2 0026 D3D2 002A D3D2 002E D0B2 0010 
0160 D032 00D0 4303 3FFC 4030 805E 4030 
8062 3FFF 0000 0000 0000 0000 0000 0000 
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
......
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 8000 (Line 2048)

The DMEM is 1KB including high(512B RAM) and low(512B RAM).

I run all the programs(5 in total).The error result as follows:
tar_nxt is no assigned to tar.
else if  (tar_clk & ~dbg_freeze) tar <=  tar_nxt;did't work.

When i use other programes to run the openMSP430 in the LPM0 mode,the tar count  and the interrupts are generated normally.But the GPIO have no output namely the final result is wrong.

Where is wrong in my process? I need your help !
Thanks a lot!

Question about TIMERA

Hi ,

While compiling the code the in Xilinx ISE , I got the following error

ERROR:HDLCompiler:267 - "D:\S2S\SVN\opencores\openmsp430\fpga\xilinx_custom_lx9board\rtl\verilog\omsp_uart.v" Line 300: Cannot find port data_meta on this module

It appears that the omsp_sync_cell module dont have the port "data_meta"

Thansk

data_meta port is not in omsp_sync_cell

In the frontend module, if there is a pending irq_acc the inst_nmi can be unconditionally cleared causing the nmi interrupt to hang as it never gets serviced. Depending on application this might be rare but in our application it's highly repeatable though there's only a 1 clock window of failure.

reg         inst_nmi;
always @(posedge mclk or negedge puc_rstn)
  if (~puc_rstn)               inst_nmi <= 1'b0;
  else if (nmi_evt)            inst_nmi <= 1'b1;
else if (i_state==I_IRQ_DONE)  inst_nmi <= 1'b0;

We fixed this by creating a signal delayed by one clock based on irq_acc as follows;

eg         irq_acc_delay;
always @(posedge mclk or negedge puc_rstn)
  if (~puc_rstn)                irq_acc_delay <= 1'b0;
  else                          irq_acc_delay <= |(irq_acc);

reg         inst_nmi;
always @(posedge mclk or negedge puc_rstn)
  if (~puc_rstn)                                  inst_nmi <= 1'b0;
  else if (nmi_evt)                               inst_nmi <= 1'b1;
  else if (i_state==I_IRQ_DONE && !irq_acc_delay) inst_nmi <= 1'b0;

The fix is working through extensive simulations which shmoo the interrupts across each other.

NMI int inadvertently masked by int_acc

Dear all;
I m trying simulating the openmsp430 with modelsim SE and linux, the simprim and unisim libraries are from ISE 13.4 version. Unfortunately I m getting the following error:
Error ./omsp_uart.v vopt-2135 Too many ports connections, expected 4 found 5.
I ve tried putting off voptflow but still got the same problem.
Please give a hand
Thanks

vopt-2135 error

It seems that the generation of pmem.sh is somehow corrupted.

pmem.sh corrupted

Hi Olivier.

First of all, really impressive and great project. Thanks you so much for sharing it to the open community.

I've might have found a minor bug when simulation the omsp430. Running the bash script named run, located at /trunk/core/sim/rtl_sim/run/, outputs the error:
pmem.sh: line 1: include: command not found.

When looking into pmem.sh the first line is:
include "openMSP430_undefines.v" 

So somehow this line of text has found its way into pmem.sh. I've noticed that msp430-gcc is used to generate pmem.sh; I'm using msp430gcc version 4.6.3 and OpenMSP430 revision 190.

Hope this can help.

Best regards

Kasper Andersen

Hello to all,

i need a good idea ..

i added the uart0 to the basic project but , in order to make it similar to msp430 uart0, i decided to use IE1 and IFG1 registers

these registers are placed into sfr code, so i needed to change it.

how can i keep and merge my new sfr file also with new omsp430 version ?

do i need to make a branch to OC server ?  or do i need to merge each time the new versions ?

thanks for your help

a second idea is coming from the request to make a demo for a MachXO2-7000 device.

i'd like to use real flash to be used as code-memory but maybe i will need to freeze the cpu waiting for slow flash info ...

since we do not able to place  a wait cycle to the program bus i think the only way is to stop the cpu clock ... is this right ?

Enrico

simple upgrade

When DBG_RST_BRK_EN is defined, the CPU starts with pmem_cen=0 and halt_flag=1 as reset values. The CPU still makes a program memory access to fetch the reset vector (from a likely not initialized memory area) and updates the PC value with it.

The PC is corrupted and the CPU has to be reset after the program memory is loaded.

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