Username:
Password:
Remember me
Register
Browse
Projects
Forums
About
Mission
Logos
Community
Statistics
HowTo/FAQ
FAQ
Project
SVN
WISHBONE
EDA Tools
Media
News
Articles
Newsletter
Licensing
Commerce
Shop
Advertise
Jobs
Partners
Maintainers
Contact us
Public Profile of job, steve
Info
Username
zigdn
Fullname
job, steve
Email
zigdn@openco... (@opencores.org)
Country
United States
Starred projects
27
Generic AHB master stub
Generic AHB slave stub
APB to SPI
APB to I2C
Generic APB master stub
Generic APB slave stub
Asynchronous SPI master
Generic AXI DMA
Generic AXI master stub
Generic AXI slave stub
Bus Transaction Monitor with JTAG
AHB DMA 32 / 64 bits
AXI DMA 32 / 64 bits
Ethernet MAC 10/100 Mbps
10G Ethernet MAC
I2C controller core
I2C master/slave Core
JTAG Test Access Port (TAP) Verilog
Open JTAG project
PCI bridge
Quad SPI Flash Controller
Generic AXI to AHB bridge
Generic AXI to APB bridge
sd card controller
8/16/32 bit SDRAM Controller
SoM-ARM9-CycloneIVGX
Ethernet 10GE MAC
Submitted bugs
29
Open
24
Open
Radix-4 Reciprocal Square Root, Division and Square Root IP Core — No files
Open
UART to Bus — Parameter Calculation Formula Questions
Open
vhdl core of IC6821 — ERROR
Open
8080 Compatible CPU — Typo in m8080.v and sm8080.v
Open
openMSP430 — Incorrect cycle length for CALL #N
Open
Generic Booth Multiplier — downloaded file is empty
Open
a VHDL 16550 UART core — RX Fifo Counter
Open
BTCMiner - Open Source Bitcoin Miner — Syntax Errors inside "sha_256_pipes2.v file"
Open
SPI Verilog Master & Slave modules — Issue when implementing on Double FPGA
Open
SHA3 (KECCAK) — SHA 3-512: This verilog code is not providing correct Hash code. Request for Correct Hash Code
Open
CPU Lecture — Compiled Code to Manipulate Array Breaks CPU
Open
AES — AES Decryption
Open
PCI bridge — PCI bridge license
Open
CAN Protocol Controller — CAN protocol controller license
Open
Next186 SoC PC — Some enhancements
Open
Simple UART for FPGA — Tx Doubled First Byte
Open
MC6803/6801 CPU — Undocumented opcode support
Open
1G eth UDP / IP Stack — IPv4_RX.vhd erroneously accepts if any part of IP address is 0xff
Open
Basic RSA Encryption Engine — Download and browse fail
Open
AES — AES Code
Open
NanoBlaze: the expandable processor — Syntax error - file nanoProcessor
Open
SHA3 (KECCAK) — Hash not work correctly as SHA3-512
Open
System09 — Download Link is Broken (Case Sensitive, should be System09 not system09)
Open
SPI Master/Slave Interface — i need more than one slave select wt modification should be done ?
Closed
5
Closed
cpu65c02_tc - R65C02 Processor Soft Core with accurate timing — VP
Closed
NoC based MPSoC — Installaion Problem
Closed
FT816Float - Floating point accelerator — module vtdl missing ?
Closed
RV01 RISC-V core — pkg missing
Closed
Attiny Atmega Xmega core — PULLUP seems to be not defined
© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.