OpenCores
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Arithmetic core 106

ProjectFilesStatisticsStatusLicenseWishbone version
1 bit adpcm codecYesStats
LGPL
2D FHTYesStats
LGPL
4-bit systemYesStats
LGPL
5x4Gbps CRC generator designed with standard cellsYesStats
Done
GPL
8 bit Vedic MultiplierYesStats
Done
LGPL
Adder libraryYesStats
Others
AES128YesStats
Done
LGPL
ANNYesStats
LGPL
Anti-Logarithm (square-root), base-2, single-cycleYesStats
Done
LGPL
BCD adderYesStats
LGPL
Binary to BCD conversions, with LED display driverYesStats
Bluespec SystemVerilog Reed Solomon DecoderYesStats
LGPL
Booth Array MultiplierYesStats
LGPL
cavlc decoderYesStats
Done
LGPL
Cellular Automata PRNGYesStats
Done
BSD
CF CordicYesStats
CF FFTYesStats
CF Floating Point MultiplierYesStats
Complex Arithmetic OperationsYesStats
LGPL
Complex Gaussian Pseudo-random Number GeneratorYesStats
LGPL
Complex MultiplierNoStats
LGPL
Complex Operations ISE for NIOS IIYesStats
LGPL
configurable cordic core in verilogYesStats
Done
configurable CRC coreYesStats
LGPL
Configurable Parallel ScramblerYesStats
Done
LGPL
CORDIC arctangent for IQ signalsYesStats
LGPL
*CORDIC coreYesStats
Done
OpenCores Certified Project
GPL
CRCAHBYesStats
LGPL
cr_div - Cached Reciprocal DividerYesStats
LGPL
DCT - Discrete Cosine TransformerYesStats
Discrete Cosine Transform coreYesStats
Done
double_fpu_verilogYesStats
Done
LGPL
DVB-S2 LDPC DecoderYesStats
LGPL
*Elliptic Curve GroupYesStats
Done
OpenCores Certified Project
LGPL
Fixed Point Arithmetic ModulesYesStats
Done
LGPL
Fixed Point Math Library for VerilogYesStats
Done
LGPL
Fixed Point Square Root (Recursive Algorithm)YesStats
LGPL
Fixed-point quadratic polynomialYesStats
GPL
Floating Point Adder and MultiplierYesStats
Done
Floating-Point Logarithm Unit YesStats
LGPL
FPGA-based Median FilterYesStats
LGPL
FPUYesStats
FPU Double VHDLYesStats
Done
FT816Float - Floating point acceleratorYesStats
LGPL
Gaussian Noise GeneratorYesStats
Done
LGPL
Generic Booth MultiplierNoStats
LGPL
Generic Galois LFSRYesStats
Done
LGPL
Generic LFSR GeneratorYesStats
LGPL
GNExtrapolatorYesStats
Done
LGPL
Hardware Division UnitsYesStats
Hardware implementation of Binary Fully Digital Phase Locked LoopYesStats
LGPL
Hardware Load Balancer for Multi-Stage Software RouterYesStats
LGPL
HCSA adder and Generic ALU based on HCSAYesStats
Heap sorter for FPGAYesStats
BSD
HIERARCHICAL Integer Multiplier unitYesStats
Huffman DecoderYesStats
Others
LCD162B Behavior ModelYesStats
LGPL
LFSR-Random number generatorYesStats
Done
LGPL
Logarithm function, base-2, single-cycleYesStats
Done
LGPL
LZRW1 Compressor CoreYesStats
Done
Wishbone Compliant
GPL
Maximum/Minimum binary tree finderYesStats
Done
LGPL
MESI Coherency InterSection ControllerYesStats
LGPL
mod3_calcYesStats
LGPL
MODBUS Implementation in VHDLYesStats
LGPL
Model of hybrid classical-quantum computing methodNoStats
Others
Multiplier libraryYesStats
Others
Multiply-Accumulate Operation (MAC)YesStats
LGPL
Non Linear Pseudo Random GeneratorYesStats
Others
Numbert sort device O(N)YesStats
Done
LGPL
openFPU64YesStats
GPL
Parameterizable adder treeYesStats
LGPL
Parameterizable integer square root by the digit-by-digit methodYesStats
LGPL
Parametrized FFT engineYesStats
BSD
PID ControlerYesStats
LGPL
pipeline mips in vhdlYesStats
GPL
Population Counter Generator YesStats
LGPL
Priority EncoderYesStats
LGPL
PYRAMID Integer Multiplier unitYesStats
QuadFixedPoint32 Arithmetic UnitYesStats
LGPL
radix 4 complex fftYesStats
Ray Tracing Arithmetic EngineYesStats
LGPL
Reconfigurable Hardware PlatformYesStats
LGPL
Reed-Solomon Decoder YesStats
Done
LGPL
RequantizerYesStats
Others
Signed / unsigned multiplier and divider with prime number generator as test circuitYesStats
Done
LGPL
Signed integer dividerYesStats
Done
LGPL
SineAndCosineTableYesStats
Done
BSD
Single 14 Segment Display Driver with Limited ASCII Decoder YesStats
LGPL
Single Clock Unsigned Division AlgorithmYesStats
Done
Special Functions Units (SFU)NoStats
New
LGPL
Superscalar Version Of DLXYesStats
LGPL
suslik scalar risc cpuYesStats
BSD
Tanh Approximation Custom Instruction for NIOS IIYesStats
LGPL
*Tate Bilinear PairingYesStats
Done
OpenCores Certified Project
LGPL
Ternary (3-input) AdderYesStats
Others
*Tiny Tate Bilinear PairingYesStats
Done
OpenCores Certified Project
Others
trigonometric functions (degrees) in double fpuYesStats
Done
LGPL
True matrix 3x3 multiplierYesStats
GPL
Universal multi-function CORDICYesStats
Others
Unsigned serial dividerYesStats
Versatile counterYesStats
Done
LGPL
Viterbi HDL Code GeneratorYesStats
Done
GPL
VIterbi_Tx_RxYesStats
Done
LGPL
Xilinx Virtex FLoating PointYesStats
LGPL
YAC - Yet Another CORDIC CoreYesStats
Done
Wishbone Compliant
LGPL
[128bit] Pseudo Random Number Generator Using Linear-feedback Shift RegistersNoStats
LGPL

Prototype board 41

Communication controller 205

Coprocessor 7

Crypto core 75

DSP core 43

ECC core 23

Library 20

Memory core 48

Other 116

Processor 208

System on Chip 80

System on Module 2

System controller 22

Testing / Verification 35

Video controller 46

Uncategorized 94