Integer Square Root |  | Stats | | LGPL | |
1 bit adpcm codec |  | Stats | | LGPL | |
2D FHT |  | Stats | | LGPL | |
4-bit system |  | Stats | | LGPL | |
5x4Gbps CRC generator designed with standard cells |  | Stats | | GPL | |
8 bit Vedic Multiplier |  | Stats | | LGPL | |
8-bit Brent-Kung Adder |  | Stats | | LGPL | |
8-bit Kogge Stone Adder |  | Stats | | LGPL | |
Adder library |  | Stats | | Others | |
AES128 |  | Stats | | LGPL | |
ANN |  | Stats | | LGPL | |
Anti-Logarithm (square-root), base-2, single-cycle |  | Stats | | LGPL | |
BCD adder |  | Stats | | LGPL | |
Binary to BCD conversions, with LED display driver |  | Stats | | | |
Bluespec SystemVerilog Reed Solomon Decoder |  | Stats | | LGPL | |
Booth Array Multiplier |  | Stats | | LGPL | |
cavlc decoder |  | Stats | | LGPL | |
Cellular Automata PRNG |  | Stats | | BSD | |
CF Cordic |  | Stats | | | |
CF FFT |  | Stats | | | |
CF Floating Point Multiplier |  | Stats | | | |
Complex Arithmetic Operations |  | Stats | | LGPL | |
Complex Gaussian Pseudo-random Number Generator |  | Stats | | LGPL | |
Complex Multiplier |  | Stats | | LGPL | |
Complex Operations ISE for NIOS II |  | Stats | | LGPL | |
Configurable AES-GCM 128-192-256 bits |  | Stats | | LGPL | |
configurable cordic core in verilog |  | Stats | | | |
configurable CRC core |  | Stats | | LGPL | |
Configurable Parallel Scrambler |  | Stats | | LGPL | |
CORDIC arctangent for IQ signals |  | Stats | | LGPL | |
CORDIC core |  | Stats | | GPL | |
CRCAHB |  | Stats | | LGPL | |
cr_div - Cached Reciprocal Divider |  | Stats | | LGPL | |
DCT - Discrete Cosine Transformer |  | Stats | | | |
Discrete Cosine Transform core |  | Stats | | | |
double_fpu_verilog |  | Stats | | LGPL | |
DVB-S2 LDPC Decoder |  | Stats | | LGPL | |
Elliptic Curve Group |  | Stats | | LGPL | |
Fixed Point Arithmetic Modules |  | Stats | | LGPL | |
Fixed Point Math Library for Verilog |  | Stats | | LGPL | |
Fixed Point Square Root (Recursive Algorithm) |  | Stats | | LGPL | |
Fixed-point quadratic polynomial |  | Stats | | GPL | |
Floating Point Adder and Multiplier |  | Stats | | | |
Floating-Point Logarithm Unit |  | Stats | | LGPL | |
floating_point_unit |  | Stats | | LGPL | |
FPGA-based Median Filter |  | Stats | | LGPL | |
FPU |  | Stats | | | |
FPU Double VHDL |  | Stats | | | |
FT816Float - Floating point accelerator |  | Stats | | LGPL | |
Gaussian Noise Generator |  | Stats | | LGPL | |
Generic Booth Multiplier |  | Stats | | LGPL | |
Generic Galois LFSR |  | Stats | | LGPL | |
Generic LFSR Generator |  | Stats | | LGPL | |
Generic Parameterized Carry Look ahead adder |  | Stats | | GPL | |
GNExtrapolator |  | Stats | | LGPL | |
Hardware Division Units |  | Stats | | | |
Hardware implementation of Binary Fully Digital Phase Locked Loop |  | Stats | | LGPL | |
Hardware Load Balancer for Multi-Stage Software Router |  | Stats | | LGPL | |
HCSA adder and Generic ALU based on HCSA |  | Stats | | | |
Heap sorter for FPGA |  | Stats | | BSD | |
Hello Digital World Counter |  | Stats | | LGPL | |
HIERARCHICAL Integer Multiplier unit |  | Stats | | | |
Huffman Decoder |  | Stats | | Others | |
LCD162B Behavior Model |  | Stats | | LGPL | |
LFSR-Random number generator |  | Stats | | LGPL | |
Logarithm function, base-2, single-cycle |  | Stats | | LGPL | |
LZRW1 Compressor Core |  | Stats | | GPL | |
Matrix multiplication and inversion |  | Stats | | LGPL | |
Maximum/Minimum binary tree finder |  | Stats | | LGPL | |
Memory Polynomial Model for Digital Predistortion |  | Stats | | LGPL | |
MESI Coherency InterSection Controller |  | Stats | | LGPL | |
miniled_local_dimming_algorithm |  | Stats | | LGPL | |
mod3_calc |  | Stats | | LGPL | |
MODBUS Implementation in VHDL |  | Stats | | LGPL | |
Model of hybrid classical-quantum computing method |  | Stats | | Others | |
Multiplier library |  | Stats | | Others | |
Multiply-Accumulate Operation (MAC) |  | Stats | | LGPL | |
Non Linear Pseudo Random Generator |  | Stats | | Others | |
Numbert sort device O(N) |  | Stats | | LGPL | |
openFPU64 |  | Stats | | GPL | |
Parameterizable adder tree |  | Stats | | LGPL | |
Parameterizable integer square root by the digit-by-digit method |  | Stats | | LGPL | |
Parametrized FFT engine |  | Stats | | BSD | |
PID Controler |  | Stats | | LGPL | |
pipeline mips in vhdl |  | Stats | | GPL | |
Population Counter Generator |  | Stats | | LGPL | |
Priority Encoder |  | Stats | | LGPL | |
PYRAMID Integer Multiplier unit |  | Stats | | | |
QuadFixedPoint32 Arithmetic Unit |  | Stats | | LGPL | |
radix 4 complex fft |  | Stats | | | |
Radix-4 Reciprocal Square Root, Division and Square Root IP Core |  | Stats | | Others | |
Ray Tracing Arithmetic Engine |  | Stats | | LGPL | |
Reconfigurable Hardware Platform |  | Stats | | LGPL | |
Reed-Solomon Decoder |  | Stats | | LGPL | |
Requantizer |  | Stats | | Others | |
Signed / unsigned multiplier and divider with prime number generator as test circuit |  | Stats | | LGPL | |
Signed integer divider |  | Stats | | LGPL | |
SineAndCosineTable |  | Stats | | BSD | |
Single 14 Segment Display Driver with Limited ASCII Decoder |  | Stats | | LGPL | |
Single Clock Unsigned Division Algorithm |  | Stats | | | |
Special Function Unit - Piecewise Polynomial Approximation |  | Stats | | LGPL | |
Special Functions Units (SFU) |  | Stats | | LGPL | |
stack_calculator |  | Stats | | LGPL | |
Superscalar Version Of DLX |  | Stats | | LGPL | |
suslik scalar risc cpu |  | Stats | | BSD | |
Tanh Approximation Custom Instruction for NIOS II |  | Stats | | LGPL | |
Tate Bilinear Pairing |  | Stats | | LGPL | |
Ternary (3-input) Adder |  | Stats | | Others | |
Tiny Tate Bilinear Pairing |  | Stats | | Others | |
trigonometric functions (degrees) in double fpu |  | Stats | | LGPL | |
True matrix 3x3 multiplier |  | Stats | | GPL | |
Universal multi-function CORDIC |  | Stats | | Others | |
Unsigned serial divider |  | Stats | | | |
Versatile counter |  | Stats | | LGPL | |
Viterbi HDL Code Generator |  | Stats | | GPL | |
VIterbi_Tx_Rx |  | Stats | | LGPL | |
Xilinx Virtex FLoating Point |  | Stats | | LGPL | |
YAC - Yet Another CORDIC Core |  | Stats | | LGPL | |
[128bit] Pseudo Random Number Generator Using Linear-feedback Shift Registers |  | Stats | | LGPL | |