OpenCores
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Stage:
License:
Wishbone version:

Arithmetic core 106

Prototype board 41

Communication controller 205

Coprocessor 7

Crypto core 75

DSP core 43

ECC core 23

Library 20

Memory core 48

Other 116

Processor 208

System on Chip 80

ProjectFilesStatisticsStatusLicenseWishbone version
AHB DMA 32 / 64 bitsYesStats
LGPL
ahb system generatorYesStats
Done
LGPL
AHB to Wishbone BridgeYesStats
Done
Wishbone Compliant
aoOCS - Wishbone Amiga OCS SoCYesStats
Wishbone Compliant
BSD
Arm coreYesStats
Assembler with VHDL User-defined Commands (AVUC)YesStats
Done
LGPL
Async-SDM-NoCYesStats
Done
LGPL
AXI DMA 32 / 64 bitsYesStats
LGPL
AXI4 Transactor and Bus Functional ModelYesStats
Done
LGPL
CCSDS RX_TX_SoCYesStats
Wishbone Compliant
Others
CMOD S6 SoCYesStats
Done
Wishbone Compliant
GPLB.4
CPU LectureYesStats
GPL
ECO32YesStats
BSD
Embedded 32-bit RISC uProcessor with SDRAM ControllerYesStats
Embedded FPGA CoreYesStats
EPC RFID TransponderYesStats
LGPL
Experimental Unstable CPUYesStats
Done
LGPL
*GECKO3 SoC co-design environmentYesStats
Done
Wishbone Compliant
OpenCores Certified Project
Others
GECKO4 SoC co-design environment YesStats
Others
Generic AHB matrixYesStats
LGPL
Generic APB register fileYesStats
LGPL
Generic AXI DMANoStats
LGPL
Generic AXI interconnect fabricYesStats
LGPL
Generic AXI to AHB bridgeYesStats
LGPL
Generic AXI to APB bridgeYesStats
LGPL
H2 Forth SoCYesStats
Done
Others
I2C Controller Wishbone WrapperYesStats
Wishbone Compliant
LGPL
Integrated round robin arbiterNoStats
Done
LGPL
Internal communication bus for FPGAYesStats
BSD
Keras to FPGAYesStats
LGPL
layer[2]YesStats
Done
GPL
M16C5xYesStats
Done
LGPL
MaSoCist Soc builder/simulatorHas external filesStats
Done
Wishbone Compliant
Has external files
OthersB.3
*minsocYesStats
Done
Wishbone Compliant
OpenCores Certified Project
LGPL
MP3 decoderYesStats
Next186 SoC PCYesStats
Done
LGPL
Next186MP3YesStats
LGPL
NoC based MPSoCYesStats
Wishbone Compliant
LGPL
NoC(Network-on-Chip) SimulatorYesStats
LGPL
NoCem -- Network on Chip emulatorYesStats
GPL
NoCmodelYesStats
LGPL
OC - H.264 Encoder SoCYesStats
LGPL
OMS8051 MINIYesStats
LGPL
OpenCL Board Support Package (BSP) for the Nallatech / Bittware 385A including dual 40 Gigabit Ethernet interfaces.NoStats
Others
OpenFIREYesStats
OpenSPARC-based SoCYesStats
GPL
or1200_socYesStats
Wishbone Compliant
Or1k SoC on Altera Embedded Dev KitYesStats
Wishbone Compliant
LGPL
ORPSoCHas external filesStats
Has external files
LGPL
PDP-1 reimplementationYesStats
LGPL
PIF2WBYesStats
Done
Wishbone Compliant
PLBv46 to Wishbone BridgeYesStats
Wishbone Compliant
Project Oberon with SDRAMYesStats
LGPL
PSS (Programmable Supervisor for Systems-on-Chip)YesStats
BSD
Real-time image processingYesStats
LGPL
rfid tag and readerYesStats
GPL
rtf68kSysYesStats
Wishbone Compliant
LGPL
SardMIPSYesStats
GPL
SBA - Simple Bus ArchitectureHas external filesStats
Has external files
LGPL
SimpCon - a Simple SoC InterconnectYesStats
LGPL
Simple AXI4-Lite bridges for IPbus and WishboneYesStats
Others
Soft MultiProcessor on FPGAYesStats
GPL
STORM SoCYesStats
Wishbone Compliant
GPL
System-On-Chip based on bare Rocket-chip (RISC-V ISA)YesStats
Done
Has external files
BSD
System-on-Chip Wire (SoCWire)YesStats
Done
system05YesStats
GPL
System09YesStats
GPL
Taar MicroprocessorNoStats
GPL
WB/OPB & OPB/WB Interface WrapperYesStats
Wishbone Compliant
WISHBONE BuilderYesStats
Wishbone Compliant
WISHBONE Conbus IP CoreYesStats
Wishbone Compliant
WISHBONE Conmax IP CoreYesStats
Wishbone Compliant
WISHBONE DMA/Bridge IP CoreYesStats
Wishbone Compliant
wishbone out port from b3 specYesStats
Done
Wishbone Compliant
LGPL
Wishbone System6800/01YesStats
Done
Wishbone Compliant
Wishbone to AHB BridgeYesStats
Wishbone Compliant
WishboneTK toolkitYesStats
Wishbone Compliant
XuLA2-LX25 SoCYesStats
Done
Wishbone Compliant
GPLB.4
Z80 System on ChipYesStats
Zorro bus to Wishbone bridgeYesStats
Wishbone Compliant
LGPL

System on Module 2

System controller 22

Testing / Verification 35

Video controller 46

Uncategorized 94