Public Profile of Kalasky, Matt
Info
| Username | 00mjk |
| Fullname | Kalasky, Matt |
| 00mjk@openco... (@opencores.org) | |
| Country | United States |
Starred projects 129
- 10/100M Ethernet-FIFO convertor
- 16x2 LCD controller
- 2D Game Console on Altera DE2-115
- 4 tap FIR Filter
- 8 bit Vedic Multiplier
- AC 97 Controller IP Core
- AcNN
- ACEX 1K50 board
- AES Decryption Core for FPGA
- AHBmaster for FPGA of microsemi
- Simple All Digital FM Receiver
- alt_ISA
- Amber ARM-compatible core
- ao486
- AES128
- arduFPGA iCE40UP5K
- ARM4U
- ANN
- ASPIDA sync/async DLX Core
- fast behavioral transceiver simulation models
- 1 bit adpcm codec
- Basic DES Crypto Core
- Configurable BCH Encoder and Decoder
- bit-serial
- Boost Converter
- CAN Protocol Controller
- CFI flash controller
- Computer Operating Properly
- Arm core
- CPU Lecture
- Cray-2 Reboot
- DarkRISCV
- Double Clocked FFT Core
- DDR SDRAM Controller Core
- AHB DMA 32 / 64 bits
- EtraxFS & Xilinx FPGA dev board with building blocks
- EP2C35 Board
- 10_100_1000 Mbps tri-mode ethernet MAC
- Linux & Xilinx FPGA Dev Board
- EUS FS - Alice II - Embeddable Single Board Computer
- fixed_extensions
- FlexGripPlus General Purpose Graphics Processing Unit (GPGPU) core
- H2 Forth SoC
- ForwardCom
- FPO (Logic Analyzer)
- Configurable Hamming Generator
- HDL-deflate
- HIVE - a 32 bit, 8 thread, 4 register/stack hybrid, pipelined verilog soft processor core
- I2C controller core
- I2C Slave
- I2C master/slave Core
- I2C Controller Wishbone Wrapper
- i8255 realisation in Verilog
- intel 8031
- Monochrome Text-Mode VGA Video Display Adapter
- Ion - MIPS(tm) compatible CPU
- JPEG Hardware Compressor
- JPEG Encoder Verilog
- KCPSM3 Maskable Interrupt
- LFSR-Random number generator
- Low Power FIR Filter
- PCI card with Xilinx X3CS500E
- Matrix Determinant Processor
- Memory Controller IP Core
- Micro FPGA Board
- miniMIPS Superscalar
- MIX-fpga
- (M)JPEG Decoder
- Milkymist One interactive VJ station
- Simple RS232 UART
- 2Q cache
- NEO430 Processor (MSP430-compatible)
- The NEORV32 Processor (RISC-V)
- Neutal Net Perceptron for Pattern Recognition
- Nios II Custom Instructions
- NoCem -- Network on Chip emulator
- ODESS Multicore Project
- OMRP Prototype board v2
- WB/OPB & OPB/WB Interface Wrapper
- Open8 uRISC
- OpenArty
- openHMC
- OpenRisc 1200 HP, Hyper Pipelined OR1200 Core
- OpenRISC 1000
- OpenRISC 1000 (old)
- OpenRISC 2000
- Plasma - most MIPS I(TM) opcodes
- Power Supply Sequencer
- Quad SPI Flash Controller
- RAM_wb
- risc16f84
- System-On-Chip based on bare Rocket-chip (RISC-V ISA)
- Random Number Generator Library
- Register Oriented Instruction Sets
- Real-time Clock
- S1 Core
- CMOD S6 SoC
- 16-bit SDRAM Controller
- SBA - Simple Bus Architecture
- SPI core
- SoM-ARM9-CycloneIVGX
- OpenSPARC-based SoC
- SPI Master/Slave Interface
- SPI Verilog Master & Slave modules
- Small x86 subset core
- Taar Microprocessor
- Theia: ray graphic processing unit
- AES cores (compact)
- CPU Code Execution Timestamp
- Technologic Systems TS-7300 FPGA Computer
- 1G eth UDP / IP Stack
- ULPI Wrapper
- uRisc-V
- USB 2.0 Function Core
- USB Device Core
- USB-FPGA Module 2.16
- VLIW Processor
- PDP-11/70 CPU core and SoC
- Pipelined wishbone to AXI converter
- Another Wishbone Controlled UART
- sp_ram to 3p_ram WISHBONE Wrapper
- WISHBONE Builder
- XuLA2-LX25 SoC
- YACC-Yet Another CPU CPU
- ZAP
- Zet - The x86 (IA-32) open implementation
- Zip Cpu
- ZPU - the worlds smallest 32 bit CPU with GCC toolchain
- ztachip
Submitted bugs 29
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