OpenCores
Written in:
Stage:
License:
Wishbone version:

Arithmetic core 119

Prototype board 42

Communication controller 218

ProjectFilesStatisticsStatusLicenseWishbone version
10/100M Ethernet-FIFO convertorYesStats
LGPL
100 MB/s Ethernet MAC Layer SwitchYesStats
LGPL
1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)YesStats
Done
LGPL
10G Ethernet MACYesStats
10_100_1000 Mbps tri-mode ethernet MACYesStats
Done
LGPL
16 Quadrature Amplitude Modulator and DemodulatorYesStats
GPL
1G eth UDP / IP StackYesStats
Done
BSD
1G Ethernet ARPYesStats
LGPL
1G Ethernet DPIYesStats
Done
LGPL
8b10b Encoder/DecoderYesStats
Done
GPL
a VHDL 16550 UART coreYesStats
Done
A VHDL CAN Protocol ControllerYesStats
Done
adat receiverYesStats
ahciHas external filesStats
Has external files
LGPL
AMI / HDB1 Line CodesYesStats
Another SPI Controller (with FIFO)Has external filesStats
Has external files
LGPL
Another Wishbone Controlled UARTYesStats
Done
Wishbone Compliant
GPLB.4
APB to I2CYesStats
LGPL
APB to SPI YesStats
LGPL
apb_protocolNoStats
LGPL
ARINC 429 Transmitter and ReceiverYesStats
Done
Others
Async 8b/10b enc/decYesStats
LGPL
Asynchronous SPI masterYesStats
Done
LGPL
Automatic BAUD rate generatorYesStats
baud generatorYesStats
GPL
Bitwise addressable GPIOYesStats
LGPL
Bluespec 802.11a TransmitterYesStats
LGPL
Bluetooth baseband controllerYesStats
Wishbone Compliant
CAN Protocol ControllerYesStats
Wishbone Compliant
Cheap Ethernet interfaceYesStats
LGPL
Classic NES controller interfaceYesStats
LGPL
Core1990: Interlaken protocolYesStats
LGPL
DMT TransceiverYesStats
GPL
DMX512 transceiverYesStats
Done
GPL
Documented Verilog UARTYesStats
Others
DQPSK MapperYesStats
GPL
E1 Framer/DeframerYesStats
E1-G.703,G.704,G.706 framer/deframerYesStats
EBU/spdif to I2S projectYesStats
Done
EPP v1.9YesStats
Etherblade.net - FPGA ethernet line-rate encapsulator (EoIP, EoMPLS, PBB etc)NoStats
LGPL
Ethernet 100/1000 Mbps YesStats
Wishbone Compliant
LGPL
Ethernet 10GE Low Latency MACYesStats
LGPL
*Ethernet 10GE MACYesStats
Done
Wishbone Compliant
OpenCores Certified Project
LGPL
*Ethernet MAC 10/100 MbpsYesStats
Done
Wishbone Compliant
OpenCores Certified Project
LGPL
Ethernet SMIIYesStats
Ethernet Switch on Configurable LogicYesStats
Done
LGPL
EZUSB communication coreYesStats
GPL
Fade - Light L3 Ethernet protocol for transmission of data from FPGA to embedded PCYesStats
Others
FireWire (IEEE 1394)YesStats
Wishbone Compliant
FPGA Communication FrameworkYesStats
BSD
FPGA remote slow control via UART 16550YesStats
Done
LGPL
FT2232H USB Avalon CoreYesStats
Others
FT245R interfaceYesStats
Done
LGPL
FTDI Async FIFO I/F to Wishbone BridgeYesStats
GPL
FTDI FT60x USB3.0 to AXI bus masterYesStats
GPL
full ethernet gigabit udp and macYesStats
CERN-OHL2-P
GamepadsYesStats
GPL
General-Purpose I/O (GPIO) CoreYesStats
Wishbone Compliant
GPIB (IEEE-488) controllerYesStats
Done
GPL
Hardware Assisted IEEE 1588 IP CoreYesStats
Done
Wishbone Compliant
LGPL
HDB3/B3ZS Encoder+DecoderYesStats
BSD
HDLC controllerYesStats
Wishbone Compliant
Hermes-Lite 2 SDR CoreNoStats
LGPL
HyperTransport TunnelYesStats
Done
*I2C controller coreYesStats
Done
Wishbone Compliant
OpenCores Certified Project
BSDB.3
I2C Master Slave CoreYesStats
Done
BSD
I2C master/slave CoreYesStats
Wishbone Compliant
I2C Multiple Bus ControllerYesStats
Done
Wishbone Compliant
BSD
I2C RepeaterYesStats
LGPL
I2C SlaveYesStats
Done
GPL
I2C Traffic LoggerYesStats
i2cgpioYesStats
LGPL
i2c_to_wbYesStats
Wishbone Compliant
LGPL
I2S InterfaceYesStats
Done
Wishbone Compliant
GPL
I2S to Paralell ADC/DAC controllerYesStats
GPL
I2S to Parallel InterfaceYesStats
Done
GPL
I2S to WishBoneYesStats
LGPL
i8255 realisation in VerilogYesStats
LGPL
IEEE 802.15.4 Core (physical layer)YesStats
Done
GPL
IEEE 802.15.4 CRCYesStats
GPL
IPv4 Ethernet Packet Creator and TransmitterYesStats
GPL
IrDAYesStats
Wishbone Compliant
Iso7816_3_MasterYesStats
BSD
JTAG MasterYesStats
LGPL
JTAG Slave / BoundaryScan SlaveYesStats
LGPL
LPC ROM emulator on USB dongle FPGA core setYesStats
LGPL
lzsHas external filesStats
Has external files
LGPL
MADI ReceiverYesStats
Done
LGPL
Manchester Decoder for WirelessYesStats
LGPL
Manchester to UART converterYesStats
Manchester UARTYesStats
LGPL
Minimac - the minimalist Ethernet MACYesStats
Done
Wishbone Compliant
GPL
Minimal UART CoreYesStats
LGPL
MMIO I2CNoStats
New
LGPL
Multimicrophone InterfaceYesStats
LGPL
nec ir remote control decoderYesStats
Done
LGPL
nec_protocol_decoderNoStats
LGPL
neopixel ws2812YesStats
Others
OFDM modemYesStats
OHCI Full/Low-Speed USB Host ControllerYesStats
Wishbone Compliant
GPL
One Wire Master YesStats
LGPL
OP2P (OpenPeerToPeer Interface)YesStats
Wishbone Compliant
LGPL
OPB SPI Slave YesStats
LGPL
OPB-compatible OneWire MasterYesStats
Done
GPL
opb_usbliteYesStats
LGPL
OV7670-SCCBMasterYesStats
LGPL
PC-FPGA Communication PlatformYesStats
GPL
Pipelined wishbone to AXI converterYesStats
Done
Wishbone Compliant
GPLB.4
Playstation 2 network adaptor IC CXD9731YesStats
Done
LGPL
PLB-to-WB BridgeYesStats
Wishbone Compliant
LGPL
PS/2 Host ControllerYesStats
LGPL
PS2 CoreYesStats
Wishbone Compliant
Quad SPI Flash ControllerYesStats
Done
Wishbone Compliant
GPLB.4
Quadrature Decoder / CounterYesStats
GPL
RapidIO IP libraryYesStats
LGPL
RS232YesStats
LGPL
RS232YesStats
Wishbone Compliant
LGPL
rtfSimpleUartYesStats
Done
Wishbone Compliant
BSD
RXAUI Interface and XAUI to RXAUI Interface AdapterYesStats
Done
SATA 2 HOST ControllerNoStats
LGPL
SATA ControllerYesStats
Others
SATA controller based on Xilinx FPGA GTX gigabit transceiverNoStats
LGPL
SATA PHYYesStats
LGPL
SaturnYesStats
LGPL
Scan Based Serial CommunicationYesStats
BSD
*sd card controllerYesStats
Done
Wishbone Compliant
OpenCores Certified Project
LGPL
SD/eMMC/MMC card emulatorYesStats
LGPL
SD/MMC BootloaderYesStats
Done
GPL
SD/MMC ControllerYesStats
Done
Wishbone Compliant
GPL
SDHC Self Configuring CoreYesStats
BSD
SDRAM AXI4YesStats
GPL
Serial ATA Host Bus Adapter Core for Virtex 6YesStats
Done
GPL
Serial to parallel converterNoStats
LGPL
Serial UARTYesStats
Serial UartYesStats
Wishbone Compliant
Serializer / Deserializer for audio fiber opticYesStats
Done
LGPL
SGMIIYesStats
Done
GPL
Simple AES3 / SPDIF receiverYesStats
Done
LGPL
Simple Asynchronous Serial ControllerYesStats
Simple RS232 UARTYesStats
Done
GPL
Simple UART for FPGAYesStats
Others
Single Slot PCM InterfaceYesStats
*Small 1-wire (onewire) master, with Altera tools integrationYesStats
Done
Wishbone Compliant
OpenCores Certified Project
LGPL
Smartcard interface (ISO7816-3)YesStats
smbus_ifYesStats
Wishbone Compliant
SpaceWireYesStats
Wishbone Compliant
LGPL
SpaceWire LightYesStats
Done
GPL
SpaceWireSystemCYesStats
Done
Others
SPDIF InterfaceYesStats
Done
Wishbone Compliant
LGPL
SPDIF TransmitterYesStats
GPL
SPI based SD card controllerYesStats
Done
Wishbone Compliant
GPLB.4
SPI controller coreYesStats
Wishbone Compliant
SPI Controller for AD/DA chips on S3E/A/AN Starter KitsYesStats
LGPL
SPI coreYesStats
Done
Wishbone Compliant
SPI Flash controllerYesStats
Done
GPL
SPI Master LightweightYesStats
Done
LGPL
spi master receiver for ADC (AD747x)YesStats
Done
LGPL
SPI Master/Slave InterfaceYesStats
Done
LGPL
SPI serial DAC interfaceYesStats
LGPL
SPI Verilog Master & Slave modulesYesStats
LGPL
SPI-slave Wishbone-MasterYesStats
Wishbone Compliant
LGPLB.4
spigpioYesStats
LGPL
spislaveYesStats
LGPL
SPIxIFYesStats
Done
LGPL
SPORT InterfaceYesStats
LGPL
SSP_SlvYesStats
Done
LGPL
SSP_UARTYesStats
Done
LGPL
Stepper Motor ControllerYesStats
GPL
Super-I/O (SIO) controllerYesStats
LGPL
SystemC USB1.1 IP CoreYesStats
Done
SystemVerilog uart16550YesStats
Wishbone Compliant
LGPL
TCP IP CoreYesStats
LGPL
TCP/IP socketYesStats
Done
Others
TDM controllerYesStats
Wishbone Compliant
TI TLV320AIC1106 PCM Codec Altera Avalon IP coreYesStats
Done
LGPL
TIME SLOT INTERCHANGE DIGITAL SWITCHYesStats
tiny SPIYesStats
Done
Wishbone Compliant
LGPL
Uart (FIFO cpu interface) with SV Self-Checking TestbenchYesStats
LGPL
UART 16550 coreYesStats
Wishbone Compliant
Uart blockYesStats
Wishbone Compliant
LGPL
UART RS232 Protocol 115200bpsNoStats
LGPL
UART to / from fiber opticYesStats
Wishbone Compliant
LGPL
*UART to BusYesStats
Done
OpenCores Certified Project
BSD
UART To SPI YesStats
LGPL
UART with PLB interfaceYesStats
LGPL
UART16750YesStats
Done
LGPL
uart6551YesStats
LGPL
UART8SYSTEMCYesStats
Done
Others
UDP 1GNoStats
LGPL
UDP half duplexNoStats
LGPL
UDP/IP CoreYesStats
GPL
UDP/IPv4 for 10G EthernetYesStats
LGPL
ULPI WrapperYesStats
BSD
USB 1.1 PHY (VHDL)YesStats
Done
LGPL
USB 1.1 Simulation (VHDL)YesStats
Done
LGPL
USB 1.1 Function IP CoreYesStats
USB 1.1 Host and Function IP coreYesStats
Done
Wishbone Compliant
LGPL
USB 1.1 PHYYesStats
USB 2.0 Function CoreYesStats
Wishbone Compliant
USB Device CoreYesStats
Done
Wishbone Compliant
LGPL
USB FT232H Avalon-MM interfaceYesStats
Done
LGPL
USB Host CoreYesStats
Done
GPL
USB to UARTYesStats
LGPL
Versatile IOYesStats
Wishbone Compliant
LGPL
via6522YesStats
BSDB.3
vSPIYesStats
Done
Others
wb_uartYesStats
Wishbone Compliant
LGPL
Wiegand Controller (SIA AC-01-1996.10)YesStats
Wishbone Compliant
LGPL
Wishbone LPC Host and Peripheral BridgeYesStats
Done
Wishbone Compliant
LGPL
Wishbone protocol to axi4 protocol YesStats
Wishbone Compliant
LGPL
Wishbone Register Bank Intercon Multi-master Multi-slaveYesStats
Done
Wishbone Compliant
BSD
Wishbone SD Card ControllerYesStats
Done
Wishbone Compliant
LGPL
wishbone uart controller 8 bitYesStats
LGPL
WishboneAXIHas external filesStats
Wishbone Compliant
Has external files
OthersB.3
*Wupper: PCIe DMA Engine for Xilinx FPGAsYesStats
Done
Wishbone Compliant
OpenCores Certified Project
OthersB.4
xSPi YesStats
LGPL
YANU - UART with predictive interrupt events on Rx/Tx buffers stateYesStats
LGPL

Coprocessor 10

Crypto core 81

DSP core 49

ECC core 24

Library 21

Memory core 51

Other 119

Processor 227

System on Chip 86

System on Module 2

System controller 21

Testing / Verification 37

Video controller 50

Uncategorized 94