16 Bit Microcontroller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
16-bit CPU based loosely on Caxton Foster's Blue architecture | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
16-bit Open uRISC core Processor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
1664 microprocessor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
32 bit Processor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
4004 CPU and MCS-4 family chips | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
6502VHDL | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
6809 and 6309 Compatible core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
68hc05 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
68hc08 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
8-BIT HARDWIRED PROCESSOR | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
8-bit microcontroller with extended peripheral set | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
8-BIT MICROPROGRAMMED PROCESSOR | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
8-bit Piepelined Processor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
8-bit uP | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
8051 core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
8080 Compatible CPU | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
A lightweight 8085 verilog implementation | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
A-Z80 CPU | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
ae18 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
aeMB | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
ag_6502 soft core with phase-level accuracy | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
AltOr32 - Alternative Lightweight OpenRisc CPU | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
alt_ISA | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Alwcpu - A light weight CPU | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Amber ARM-compatible core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
An inventory of soft processor cores | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
ao486 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
ao68000 - Wishbone 68000 core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
aoR3000 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
Apollo Guidance Computer NOR eMulator | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
Aquarius | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
ARM4U | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
AsCPro I | ![No](https://cdn.opencores.org/img/no.png) | Stats | | GPL | |
ASPIDA sync/async DLX Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Atlas Processor Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
Attiny Atmega Xmega core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
AVR Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
AVR HP, Hyper Pipelined AVR Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
AVRtinyX61core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
AX8 mcu | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
BiRiscV - 32-bit dual issue RISC-V CPU | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
bit-serial | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
Brainfuck CPU | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
CBU Graduation Project | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
CF State Space Processor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
ClaiRISC - runs 12bit opcode PIC family. | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Classic 5-Stage Pipeline MIPS | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
Codezero OpenRISC Port | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
Confluence OpenRisc 1000 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
copyBlaze | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Cowgirl | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Cpu Generator | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
cpu6502_tc - R6502 Processor Soft Core with accurate timing | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
cpu65c02_tc - R65C02 Processor Soft Core with accurate timing | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
DarkRISCV | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
Data Flow Processor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Diogenes: Student RISC System | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Distributed limited cores | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
ecpu_alu | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
Edge Processor (MIPS) | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Educational 16-bit MIPS Processor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Educational RISC Processor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
ELM Embedded Processor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
erm16 | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
Fault-Tolerant Microprocessor | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
Featherweight RISC-V | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
Fluid Core (A Reconfigurable Pipelined RISC processor) | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
FORTH processor with Java compiler | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
ForwardCom | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | CERN-OHL-L | |
FPz8 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
GPU | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
HC11 Compatible - Gator uProcessor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
HD63701 compatible core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
HF-RISC | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
HiCoVec - a configurable SIMD CPU | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
HIVE - a 32 bit, 8 thread, 4 register/stack hybrid, pipelined verilog soft processor core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
HPC-16 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
HyperMTA | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
i650 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
i8080 compatible processor using Am29XX bit slice family and microcoded design | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Ion - MIPS(tm) compatible CPU | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
JOP: a Java Optimized Processor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
K68 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
KLC32 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Lattice 6502 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
LEM1_9 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Leros-32 | ![Has external files](https://cdn.opencores.org/img/has-external-files.png) | Stats | | LGPL | |
Leros: A Tiny Microcontroller for FPGAs | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
Lightweight 8051 compatible CPU | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Lightweight 8080 compatible core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
LocationPU | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
LXP32, a lightweight 32-bit CPU core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | B.3 |
M1 Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
M32632 32-bit Processor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
M65C02 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
MB-Lite | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
MC6803/6801 CPU | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
McAdam's RISC Computer Architecture | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
MCIP open | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
MCPU - A minimal CPU for a CPLD | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
microprocessor za208 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
MicroRISC II | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
MicroSimplez | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Mini-Risc core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Minimal PDP8/L implementation with 4K disk monitor system | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
miniMIPS | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
miniMIPS Superscalar | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
mips compatible barrel processor | ![Has external files](https://cdn.opencores.org/img/has-external-files.png) | Stats | | LGPL | |
Mips-FaultTolerant | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
MIPS32 Release 1 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
MIPS32 Release 1 with support for FPU and other COPs | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
mips789 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
mipsr2000 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
MIPS_enhanced | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
MIX-fpga | ![No](https://cdn.opencores.org/img/no.png) | Stats | | GPL | |
MMU for Z80 and eZ80 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
MPX 32-bit CPU | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
MSP430 CPU core in VHDL | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
myBlaze | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
NanoBlaze: the expandable processor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Natalius 8 bit RISC | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Navré AVR clone (8-bit RISC) | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
nCore | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
NEO430 Processor (MSP430-compatible) | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | B.4 |
Next 80186 processor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
NextZ80 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
ODESS Multicore Project | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
oks8 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
OoOPs - Out-of-Order MIPS (TM) Processor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
OpenCores54x DSP | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
opencpu | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
OpenCPU32 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
OpenFire Processor Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
openMSP430 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
OpenRISC 1000 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
OpenRISC 1000 (old) | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
OpenRisc 1200 HP, Hyper Pipelined OR1200 Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
OpenRISC 2000 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
OpenTPULike | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
P16C5x | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
pAVR | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
PDP-11/70 CPU core and SoC | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
PDP-8 Processor Core and System | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
Pepelatz MISC | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Plasma - most MIPS I(TM) opcodes | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
plasma with FPU | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
Potato Processor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
PPX16 mcu | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
qrisc32 wishbone compatible risc core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
QUARK RISK | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
r2000 Soc | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Raptor64 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Reduced AVR Core for CPLD | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Register Oriented Instruction Sets | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
rf68000 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
rf6809 8/12 bit | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | B.3 |
RISC Microcontroller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
risc16f84 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
RISC5x | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
RISCOmpatible | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
RISCV-EC | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
RISC_Core_I | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
RISE Microprocessor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Rockwell PPS4-2 core | ![No](https://cdn.opencores.org/img/no.png) | Stats | | GPL | |
RTF65002 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
rtf8088 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
RV01 RISC-V core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
S1 Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
S80186 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
SAP-1 NANOPROGRAMMED PROCESSOR | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
SAP-1 VERTICAL MICROPROGRAMMED PROCESSOR | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
SAYEH educational processor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Scarts Processor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
small non-pipelined, 3 stage 16-bit cpu (fetch,decode,execute) | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Small Stack Based Computer Compiler | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
Small x86 subset core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Soft AVR Core + Interfaces | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Software Aided Wishbone Extension for Xilinx (R) PicoBlaze (TM) | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
Steel Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
Storm Core (ARM7 compatible) | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
SUBLEQ eForth CPU | ![No](https://cdn.opencores.org/img/no.png) | Stats | | BSD | |
SXP (Simple eXtensible Pipeline ) Processor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
system11 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
System68 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
T400 µController | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
T48 µController | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
T51 mcu | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
T65 CPU | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
T6507LP | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
T80 cpu | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
TG68 - execute 68000 Code | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
TG68K.C | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
The NEORV32 Processor (RISC-V) | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | B.4 |
The Neptune Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Theia: ray graphic processing unit | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
Thor Superscaler | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Tiny Instruction Set Computer | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Tiny64 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
tiny8 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
TinyCPU | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
tinyVLIW8 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
TMS1000 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
TotalCPU | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Trinary CPU "Typhoon" | ![No](https://cdn.opencores.org/img/no.png) | Stats | | GPL | |
turbo 8051 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
TV80 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
UCore | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
UoS Educational Processor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
uRisc-V | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
v586 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
V6502 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
V65C816 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
vhdl core of IC6821 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
VLIW Processor | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
VTACH - Bell Labs CARDIAC reimagined in Verilog | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Wishbone BFM | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Wishbone High Performance Z80 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Y80e - Z80/Z180 compatible processor extended by eZ80 instructions | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
YACC-Yet Another CPU CPU | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Yellow Star | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Z3 - The Zork CPU | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
Z80 Soft Core Microprocessor | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
z80control | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
Zet - The x86 (IA-32) open implementation | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
Zip Cpu | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | B.4 |
ZPU - the worlds smallest 32 bit CPU with GCC toolchain | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |