10/100M Ethernet-FIFO convertor | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
100 MB/s Ethernet MAC Layer Switch | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS) | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
10G Ethernet MAC | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
10_100_1000 Mbps tri-mode ethernet MAC | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
16 Quadrature Amplitude Modulator and Demodulator | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
1G eth UDP / IP Stack | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
1G Ethernet ARP | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
1G Ethernet DPI | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
8b10b Encoder/Decoder | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
a VHDL 16550 UART core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
A VHDL CAN Protocol Controller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
adat receiver | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
ahci | ![Has external files](https://cdn.opencores.org/img/has-external-files.png) | Stats | | LGPL | |
AMI / HDB1 Line Codes | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Another SPI Controller (with FIFO) | ![Has external files](https://cdn.opencores.org/img/has-external-files.png) | Stats | | LGPL | |
Another Wishbone Controlled UART | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | B.4 |
APB to I2C | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
APB to SPI | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
apb_protocol | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
ARINC 429 Transmitter and Receiver | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
Async 8b/10b enc/dec | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Asynchronous SPI master | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Automatic BAUD rate generator | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
baud generator | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
Bitwise addressable GPIO | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Bluespec 802.11a Transmitter | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Bluetooth baseband controller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
CAN Protocol Controller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Cheap Ethernet interface | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Classic NES controller interface | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Core1990: Interlaken protocol | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
DMT Transceiver | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
DMX512 transceiver | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
Documented Verilog UART | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
DQPSK Mapper | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
E1 Framer/Deframer | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
E1-G.703,G.704,G.706 framer/deframer | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
EBU/spdif to I2S project | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
EPP v1.9 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Etherblade.net - FPGA ethernet line-rate encapsulator (EoIP, EoMPLS, PBB etc) | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
Ethernet 100/1000 Mbps | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Ethernet 10GE Low Latency MAC | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Ethernet 10GE MAC | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Ethernet MAC 10/100 Mbps | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Ethernet SMII | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Ethernet Switch on Configurable Logic | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
EZUSB communication core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
Fade - Light L3 Ethernet protocol for transmission of data from FPGA to embedded PC | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
FireWire (IEEE 1394) | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
FPGA Communication Framework | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
FPGA remote slow control via UART 16550 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
FT2232H USB Avalon Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
FT245R interface | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
FTDI Async FIFO I/F to Wishbone Bridge | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
FTDI FT60x USB3.0 to AXI bus master | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
full ethernet gigabit udp and mac | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | CERN-OHL2-P | |
Gamepads | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
General-Purpose I/O (GPIO) Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
GPIB (IEEE-488) controller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
Hardware Assisted IEEE 1588 IP Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
HDB3/B3ZS Encoder+Decoder | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
HDLC controller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Hermes-Lite 2 SDR Core | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
HyperTransport Tunnel | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
I2C controller core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | B.3 |
I2C Master Slave Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
I2C master/slave Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
I2C Multiple Bus Controller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
I2C Repeater | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
I2C Slave | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
I2C Traffic Logger | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
i2cgpio | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
i2c_to_wb | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
I2S Interface | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
I2S to Paralell ADC/DAC controller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
I2S to Parallel Interface | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
I2S to WishBone | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
i8255 realisation in Verilog | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
IEEE 802.15.4 Core (physical layer) | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
IEEE 802.15.4 CRC | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
IPv4 Ethernet Packet Creator and Transmitter | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
IrDA | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Iso7816_3_Master | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
JTAG Master | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
JTAG Slave / BoundaryScan Slave | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
LPC ROM emulator on USB dongle FPGA core set | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
lzs | ![Has external files](https://cdn.opencores.org/img/has-external-files.png) | Stats | | LGPL | |
MADI Receiver | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Manchester Decoder for Wireless | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Manchester to UART converter | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Manchester UART | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Minimac - the minimalist Ethernet MAC | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
Minimal UART Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
MMIO I2C | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
Multimicrophone Interface | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
nec ir remote control decoder | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
nec_protocol_decoder | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
neopixel ws2812 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
OFDM modem | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
OHCI Full/Low-Speed USB Host Controller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
One Wire Master | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
OP2P (OpenPeerToPeer Interface) | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
OPB SPI Slave | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
OPB-compatible OneWire Master | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
opb_usblite | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
OV7670-SCCBMaster | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
PC-FPGA Communication Platform | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
Pipelined wishbone to AXI converter | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | B.4 |
Playstation 2 network adaptor IC CXD9731 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
PLB-to-WB Bridge | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
PS/2 Host Controller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
PS2 Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Quad SPI Flash Controller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | B.4 |
Quadrature Decoder / Counter | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
RapidIO IP library | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
RS232 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
RS232 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
rtfSimpleUart | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
RXAUI Interface and XAUI to RXAUI Interface Adapter | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
SATA 2 HOST Controller | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
SATA Controller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
SATA controller based on Xilinx FPGA GTX gigabit transceiver | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
SATA PHY | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Saturn | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Scan Based Serial Communication | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
sd card controller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
SD/eMMC/MMC card emulator | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
SD/MMC Bootloader | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
SD/MMC Controller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
SDHC Self Configuring Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
SDRAM AXI4 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
Serial ATA Host Bus Adapter Core for Virtex 6 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
Serial to parallel converter | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
Serial UART | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Serial Uart | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Serializer / Deserializer for audio fiber optic | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
SGMII | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
Simple AES3 / SPDIF receiver | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Simple Asynchronous Serial Controller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Simple RS232 UART | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
Simple UART for FPGA | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
Single Slot PCM Interface | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Small 1-wire (onewire) master, with Altera tools integration | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Smartcard interface (ISO7816-3) | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
smbus_if | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
SpaceWire | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
SpaceWire Light | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
SpaceWireSystemC | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
SPDIF Interface | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
SPDIF Transmitter | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
SPI based SD card controller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | B.4 |
SPI controller core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
SPI Controller for AD/DA chips on S3E/A/AN Starter Kits | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
SPI core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
SPI Flash controller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
SPI Master Lightweight | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
spi master receiver for ADC (AD747x) | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
SPI Master/Slave Interface | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
SPI serial DAC interface | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
SPI Verilog Master & Slave modules | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
SPI-slave Wishbone-Master | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | B.4 |
spigpio | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
spislave | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
SPIxIF | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
SPORT Interface | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
SSP_Slv | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
SSP_UART | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Stepper Motor Controller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
Super-I/O (SIO) controller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
SystemC USB1.1 IP Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
SystemVerilog uart16550 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
TCP IP Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
TCP/IP socket | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
TDM controller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
TI TLV320AIC1106 PCM Codec Altera Avalon IP core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
TIME SLOT INTERCHANGE DIGITAL SWITCH | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
tiny SPI | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Uart (FIFO cpu interface) with SV Self-Checking Testbench | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
UART 16550 core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
Uart block | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
UART RS232 Protocol 115200bps | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
UART to / from fiber optic | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
UART to Bus | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
UART To SPI | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
UART with PLB interface | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
UART16750 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
uart6551 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
UART8SYSTEMC | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
UDP 1G | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
UDP half duplex | ![No](https://cdn.opencores.org/img/no.png) | Stats | | LGPL | |
UDP/IP Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
UDP/IPv4 for 10G Ethernet | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
ULPI Wrapper | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
USB 1.1 PHY (VHDL) | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
USB 1.1 Simulation (VHDL) | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
USB 1.1 Function IP Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
USB 1.1 Host and Function IP core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
USB 1.1 PHY | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
USB 2.0 Function Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | | |
USB Device Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
USB FT232H Avalon-MM interface | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
USB Host Core | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | GPL | |
USB to UART | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Versatile IO | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
via6522 | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | B.3 |
vSPI | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | |
wb_uart | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Wiegand Controller (SIA AC-01-1996.10) | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Wishbone LPC Host and Peripheral Bridge | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Wishbone protocol to axi4 protocol | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
Wishbone Register Bank Intercon Multi-master Multi-slave | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | BSD | |
Wishbone SD Card Controller | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
wishbone uart controller 8 bit | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
WishboneAXI | ![Has external files](https://cdn.opencores.org/img/has-external-files.png) | Stats | | Others | B.3 |
Wupper: PCIe DMA Engine for Xilinx FPGAs | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | Others | B.4 |
xSPi | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |
YANU - UART with predictive interrupt events on Rx/Tx buffers state | ![Yes](https://cdn.opencores.org/img/yes.png) | Stats | | LGPL | |